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797 Commits

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Author SHA1 Message Date
Dmitry Stogov
6b8a33d726 Introduce IR Builder API 2023-02-10 13:34:46 +03:00
Dmitry Stogov
9b6b6996c4 Move IR_ALWAYS_INLINE and IR_NEVER_INLINE definition into public ir.h 2023-02-07 23:14:10 +03:00
Dmitry Stogov
6a4187eacc Fixed CLANG build 2023-02-07 23:11:16 +03:00
Dmitry Stogov
d7ed2fdfad We can't relay on block order because they are re-scheduled later 2023-02-07 03:30:44 +03:00
Dmitry Stogov
2e31446e37 Better 'jp' elimination for IR_CMP_AND_BRANCH_FP 2023-02-07 01:57:07 +03:00
Dmitry Stogov
6521c0b7e4 Better 'jp' elimination for GUARDs 2023-02-07 01:06:30 +03:00
Dmitry Stogov
02104b0950 Add XFAIL-ed test for a non-efficient register allocation that should be improved 2023-02-07 00:06:53 +03:00
Dmitry Stogov
aada927840 Add type checks for LOAD/STORE and VLOAD/VSTORE 2023-02-07 00:05:59 +03:00
Dmitry Stogov
1773bb81aa Make a decision about load fusion and operand swapping together 2023-02-05 14:48:14 +03:00
Dmitry Stogov
cfc959d8ca Better load fusion 2023-02-03 12:50:00 +03:00
Dmitry Stogov
dc728853a2 JMP optimization for GUARDs (guard failur is unexpected) 
TODO: this should be ported to ARM
 2023-02-01 14:51:36 +03:00
Dmitry Stogov
743696fe03 Simplify condition 2023-01-31 16:15:08 +03:00
Dmitry Stogov
038b1e43cd We can't preallocate stack for fastcall function calls 2023-01-31 16:13:15 +03:00
Dmitry Stogov
58ba18bb7d Fix ir_test and set proper initial SP offset info for GDB backtraces 2023-01-31 11:51:55 +03:00
Dmitry Stogov
677c6cb2cb Move declaration of some register alloation related macros to public API 
Use RLOAD.op3 as a flag to avoid spill store
 2023-01-30 16:33:57 +03:00
Dmitry Stogov
bbfcb3e8c8 Fix register allocation for MUL_OV in a different way 2023-01-26 13:20:08 +03:00
Dmitry Stogov
4fb50d85aa Add assertion when allocated preserved register is not saved in "fixed" frame prologue 2023-01-26 12:49:23 +03:00
Dmitry Stogov
761c50488e Fix incorrect code generation 2023-01-26 11:50:10 +03:00
Dmitry Stogov
4a67399005 Fix integer MUL overflow checks 2023-01-26 10:08:40 +03:00
Dmitry Stogov
0eff9e0516 Registers %r4b - %r7b are not available in 32-bit mode 2023-01-24 15:31:31 +03:00
Dmitry Stogov
01c4b95c18 Fix test for empty ENTRY block 2023-01-24 11:59:41 +03:00
Dmitry Stogov
771da56d07 Fix incorrect tests for empty basic blocks 2023-01-24 11:48:21 +03:00
Dmitry Stogov
a5c0514b13 Use better conditions 2023-01-23 16:05:06 +03:00
Dmitry Stogov
169033c291 RETURN may be followed by ENTRY 2023-01-23 16:04:11 +03:00
Dmitry Stogov
afc948def6 Fix 32-bit negation 2023-01-20 16:00:23 +03:00
Dmitry Stogov
32ad3d1052 Use inline functions to avoid false positive address sanitaizer warnings 2023-01-20 15:35:02 +03:00
Dmitry Stogov
3ac58893f2 Fix address sanitizer warnings 2023-01-20 11:30:22 +03:00
Dmitry Stogov
8c715480e3 Fix disassembler. Allow ENTRY references in jump tables. 2023-01-20 09:13:15 +03:00
Dmitry Stogov
5103c18269 Fix load fusion in combination with depended register spill load 2023-01-19 13:39:29 +03:00
Dmitry Stogov
a85f59a62d Fix MERGE to BEGIN conversion in SCCP 2023-01-19 10:08:48 +03:00
Dmitry Stogov
4bc47db08d Fix use_list update 2023-01-18 17:19:37 +03:00
Dmitry Stogov
29da69cf25 Fix CASE_VAL scheduling (mark op2 as used constant). 2023-01-18 09:38:18 +03:00
Dmitry Stogov
211677e2c2 Add check for SWITCH targets 2023-01-18 09:37:30 +03:00
Dmitry Stogov
397ed1696b Split at "max_pos" if "min_bb" is in a deeper loop than "max_bb" 2022-12-29 01:39:24 +03:00
Dmitry Stogov
208e0040ae Prefer 'ADD [addr], %r1' over 'mov [addr], %r1; lea [%r1, %r2], %r3' 2022-12-28 22:24:42 +03:00
Dmitry Stogov
e710f30170 Constant folding for MUL_OV 2022-12-28 09:10:39 +03:00
Dmitry Stogov
e067ff66f3 Allow fuse load of constant address 2022-12-28 09:10:16 +03:00
Dmitry Stogov
b043955723 First opernad of IMUL3 can not be constant 2022-12-28 09:09:19 +03:00
Dmitry Stogov
54597bc862 Clear destination regeister before INT to FP conversion to avoid partial register stall 2022-12-28 00:05:23 +03:00
Dmitry Stogov
cc8f3fe987 Fix register allocation for intervals started by RLOAD of non-fixed register. 
These intervals may be split and spilled.
 2022-12-27 22:34:52 +03:00
Dmitry Stogov
d528d29872 Fix memory leaks in case of dynasm errors and JIT buffer overflow 2022-12-26 20:58:54 +03:00
Dmitry Stogov
67da9e93ea Fix register clobbering during argument passing and spill load 2022-12-26 20:25:11 +03:00
Dmitry Stogov
d26b162ffa Fix register clobbering during argument passing 2022-12-26 18:27:53 +03:00
Dmitry Stogov
9f0bf4849f Fix build 2022-12-26 14:44:57 +03:00
Dmitry Stogov
1df594fea5 Fix memory leak 2022-12-26 14:17:48 +03:00
Dmitry Stogov
844653cfd1 Fix IR reconstruction during SCCP 2022-12-23 14:34:51 +03:00
Dmitry Stogov
862e25d96c Try allocationg another blocked register in case of unresolvable conflicts 2022-12-22 22:09:04 +03:00
Dmitry Stogov
cfa8dac9d9 Fix load fusion 2022-12-21 23:32:16 +03:00
Dmitry Stogov
1bff08bc10 Update use_lists when modify an instruction 2022-12-21 23:31:11 +03:00
Dmitry Stogov
53ead9d2e7 Generate better code for GUARD(_, AND(_, _), _) 2022-12-16 15:07:18 +03:00