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698 Commits 2 Branches 0 Tags 3.2 MiB
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104 Commits

Author SHA1 Message Date
Dmitry Stogov
26e462fa42 Add more folding rules 2023-03-29 14:07:31 +03:00
Dmitry Stogov
e4b618ad00 Fix fusion of IF(_, CMP(AND(_, _) 0)) 2023-03-28 19:03:06 +03:00
Dmitry Stogov
6d36fb12c3 Fix example code and test 2023-03-23 00:54:47 +03:00
Dmitry Stogov
24e8e216a1 Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
Dmitry Stogov
ccbf3da286 Add test 2023-03-22 22:09:25 +03:00
Dmitry Stogov
1542048331 Fix TAILCALL on WIN64 2023-03-02 22:08:24 +03:00
Dmitry Stogov
29122c15c3 Add complex WIN64 tests 2023-03-02 17:57:26 +03:00
Dmitry Stogov
c89a038fd3 Fix tests with capstone 5 
Different versions of capstone may disassemble MOVD/MOVQ differentrly
 2023-03-02 17:54:50 +03:00
Dmitry Stogov
5a48805c81 Add support for Windows-64 ABI ("home space") 
Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant

TODO: ARM code maight need similar changes
 2023-03-02 13:27:01 +03:00
Dmitry Stogov
ebdeba9fff Add simple tests for Windows-x86_64 
conv_004.irt and conv_010.irt fail with capstone 5 because of changes in movd/movq
 2023-03-02 00:55:20 +03:00
Dmitry Stogov
00d5e471ad Improve load fusion, register allocateion and code selection for ADD 2023-02-21 22:55:47 +03:00
Dmitry Stogov
2f2fed89bb Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32") 2023-02-17 18:11:13 +03:00
Dmitry Stogov
1d7ab16c2a Allow load fuson for CALL and TAILCALL with arguments 2023-02-14 14:51:12 +03:00
Dmitry Stogov
2e31446e37 Better 'jp' elimination for IR_CMP_AND_BRANCH_FP 2023-02-07 01:57:07 +03:00
Dmitry Stogov
02104b0950 Add XFAIL-ed test for a non-efficient register allocation that should be improved 2023-02-07 00:06:53 +03:00
Dmitry Stogov
54597bc862 Clear destination regeister before INT to FP conversion to avoid partial register stall 2022-12-28 00:05:23 +03:00
Dmitry Stogov
67da9e93ea Fix register clobbering during argument passing and spill load 2022-12-26 20:25:11 +03:00
Dmitry Stogov
d26b162ffa Fix register clobbering during argument passing 2022-12-26 18:27:53 +03:00
Dmitry Stogov
95729f76bf Use IMUL instead of MUL 2022-12-16 12:57:40 +03:00
Dmitry Stogov
efbc51baaa Fixed codegeneration for TRUNC on aarch64 2022-12-07 11:56:53 +03:00
Dmitry Stogov
daf659a457 Fix incorrect conditions 2022-12-01 00:43:42 +03:00
Dmitry Stogov
c6aeb417fa Extend test suite to support XFAIL section 2022-11-22 10:43:29 +03:00
Dmitry Stogov
3e3746d5cb Refactor API that expose target CPU register constraints for register allocator 2022-11-17 23:30:35 +03:00
Dmitry Stogov
05127b1b13 Remove duplicate code and allow load fusion of IR_SHIFT.op2 2022-11-16 13:20:58 +03:00
Dmitry Stogov
673779ba6a Use IR_COPY_INT/FP rule instead of IR_COPY op 2022-11-16 12:55:40 +03:00
Dmitry Stogov
4c536aae20 Extend SCCP to perform Dead Load Elimination 2022-11-08 15:39:00 +03:00
Dmitry Stogov
37dececa71 Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
Dmitry Stogov
2ff0617db6 Perform iterative folding and DCE as a final pass of SCCP 2022-11-08 00:41:08 +03:00
Dmitry Stogov
924f5949f2 Fixed SSE operands alignment and 32-bit support 2022-09-27 20:36:34 +03:00
Dmitry Stogov
05fd1f971d Better LOAD fusion 2022-09-21 23:54:45 +03:00
Dmitry Stogov
69a3d6fd27 Verify type compatibility 2022-09-02 09:50:38 +03:00
Dmitry Stogov
32198c00b7 Reimplement JMP optimization 2022-08-30 23:15:20 +03:00
Dmitry Stogov
0596de2291 Fuse LOAD into IMULL/3 2022-08-30 11:26:38 +03:00
Dmitry Stogov
fd8539e17d Eliminate TEST after ADD/SUB/AND/OR/XOR 2022-08-29 22:22:30 +03:00
Dmitry Stogov
47083e0f9f Improve LOAD fusion 2022-08-25 18:16:17 +03:00
Dmitry Stogov
65e1619de8 Fuse address calculation into LOAD/STORE 2022-08-24 16:11:04 +03:00
Dmitry Stogov
32e045d93e typo 2022-08-23 17:02:34 +03:00
Dmitry Stogov
88b8731c16 Fix incorrect condition codes 2022-08-02 13:04:03 +03:00
Dmitry Stogov
9b25587eb6 Compound assignment instruction fusion 2022-06-21 17:33:57 +03:00
Dmitry Stogov
5fb115ab11 Remove LOOP_EXIT 2022-06-15 17:27:31 +03:00
Dmitry Stogov
c28fe2734d Validate operand types 2022-06-03 11:23:05 +03:00
Dmitry Stogov
ab8019e0cd Aarch64 back-end (incomplete) 2022-06-02 15:12:56 +03:00
Dmitry Stogov
bb842b489c Aarch64 backend support & unification 2022-06-01 18:16:32 +03:00
Dmitry Stogov
f5bbdeea27 Fix buffer overflow 2022-05-26 17:19:43 +03:00
Dmitry Stogov
7e782a291a Extend disassembler to support .rodata section and IP relative data labels 2022-05-26 01:17:02 +03:00
Dmitry Stogov
19e93fd3f6 Allow multi-target test suite 2022-05-25 17:38:22 +03:00
Dmitry Stogov
463002107a Rename "gcm_blocks" into "cfg_map" 2022-05-25 09:33:47 +03:00
Dmitry Stogov
04667faf22 Reorder blocks according to branch probability 2022-05-24 12:47:39 +03:00
Dmitry Stogov
d3c1e4a02f Reorder basic blocks to reduce number of jumps and improve code locality 2022-05-24 00:43:35 +03:00
Dmitry Stogov
6f7f7b1268 Implement code generation for type conversion instructions 
Register constraints might need to be tweeked.
 2022-05-20 13:07:41 +03:00