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218 Commits

Author SHA1 Message Date
Dmitry Stogov
7e710d5e91 Speedup coalescing 2022-11-16 00:40:14 +03:00
Dmitry Stogov
c8dc4e9e74 Move ir_input_edges_count(phi) out of the loop, because all PHIs inherit their arity from MERGE/LOOP_BEGIN 2022-11-09 21:54:01 +03:00
Dmitry Stogov
3535fd2fc4 Fix compilation warnings and signed/unsigned mess 2022-11-08 23:09:35 +03:00
Dmitry Stogov
cc73788981 Fix compilation warnings 2022-11-08 18:17:29 +03:00
Dmitry Stogov
cc56f12f13 Add LICENSE and copyright notices 2022-11-08 11:32:46 +03:00
Dmitry Stogov
22385c1528 Allocate and reuse spill slots using simple linear-scan (without holes) 2022-11-02 21:53:05 +03:00
Dmitry Stogov
0a5bb4a571 Better condition 2022-11-02 21:28:56 +03:00
Dmitry Stogov
802ec945ad Reorder conditions for the most common case 2022-11-02 16:27:26 +03:00
Dmitry Stogov
3af9e1a062 Move some common code into ir_emit.c 2022-10-26 22:52:19 +03:00
Dmitry Stogov
4b114914dc Prevent register clobbering 2022-10-25 12:24:05 +03:00
Dmitry Stogov
265ebc1000 Fix two LSRA edge cases 2022-10-24 21:55:59 +03:00
Dmitry Stogov
9f472c1c91 Add support for deoptimization and binding to multiple slots 2022-10-21 17:16:25 +03:00
Dmitry Stogov
22cd9265d3 Check if the register is necessary at all 2022-10-18 22:02:09 +03:00
Dmitry Stogov
3ef58e5c2e Take into account RLOADs for non fixed registers 2022-10-11 22:23:09 +03:00
Dmitry Stogov
f5c0151740 Remove hints to the same virtual register 2022-10-05 20:31:20 +03:00
Dmitry Stogov
e9402c8436 Add hint for "op1" if result reuses "op1" register. 
This improves register allocation if regiter for result was coalesced and allocated before the register for operand.
 2022-10-05 17:58:37 +03:00
Dmitry Stogov
45fff1fe5f Implement binding IR node to VAR (assign spill slot) 2022-09-20 11:03:25 +03:00
Dmitry Stogov
9aac7e76af Requre opearnad to be in register 2022-09-15 22:18:35 +03:00
Dmitry Stogov
a0c9405ae7 Fixed memory leak 2022-09-15 20:32:20 +03:00
Dmitry Stogov
e6f6e92d66 Improve spill code fusion 2022-09-15 17:52:28 +03:00
Dmitry Stogov
ad59556d85 Add support for binding IR nodes to "external" spill slots (e.g. PHP VM stack slots) 2022-09-15 15:26:43 +03:00
Dmitry Stogov
d4cd0d6eba Better interval splitting 2022-09-15 01:50:25 +03:00
Dmitry Stogov
cdc34ae22b Prohibit swapping of operands when the first operand is constant 2022-09-14 14:28:57 +03:00
Dmitry Stogov
76028e8855 Fix compilation warnings 2022-09-05 22:43:27 +03:00
Dmitry Stogov
756a1afc82 Better register allocation support for address and load fusion 2022-09-01 19:19:01 +03:00
Dmitry Stogov
b0cba142a9 Merge ir_uses_fixed_reg() into ir_get_def_flags() and ir_get_use_flags() 2022-08-12 21:17:19 +03:00
Dmitry Stogov
b607a28b2a Fix 2022-08-12 21:01:35 +03:00
Dmitry Stogov
360ca107f4 Replace dirst ir_bitset_union() by ir_bitset_copy() 2022-08-12 19:52:24 +03:00
Dmitry Stogov
d55154d998 Introduce ir_bitqueue API 2022-08-12 19:25:10 +03:00
Dmitry Stogov
9ff5d74778 Introduce ir_bitset_pop_first_ex() and ir_bitset_incl_ex() to avoid repatable checks of the first bitset elements. 2022-08-12 18:01:15 +03:00
Dmitry Stogov
253b99ae74 Eliminate useless ir_bitset_empty() checks 2022-08-11 20:42:03 +03:00
Dmitry Stogov
ca109d3fc9 Use single live interval to handle all scratch registers clobbered by CALL 2022-08-11 19:56:59 +03:00
Dmitry Stogov
1820972a21 Use PHP memory manager 2022-08-10 17:41:14 +03:00
Dmitry Stogov
825d18a5cf Reprder conditions 2022-08-10 15:37:14 +03:00
Dmitry Stogov
8ed4a4d2fa Cleanup "current_range" cache maintenance 2022-08-10 15:24:09 +03:00
Dmitry Stogov
8861c6cf54 Construct unhandled list in backward order to simplify the list sorting 2022-08-10 15:04:01 +03:00
Dmitry Stogov
1ef04d2540 Improve live interval coverage and overlaping tests by checking only the necessary tails of active and inactive intervals. 2022-08-10 13:59:34 +03:00
Dmitry Stogov
89013100c8 Optimize ir_ival_covers() (the list of live ranges is sorted) 2022-08-10 10:38:30 +03:00
Dmitry Stogov
0295c071cf Cache the last ir_live_range.end in ir_live_interval.end 2022-08-10 09:47:06 +03:00
Dmitry Stogov
2148f05392 Initial support for fascall calling convention (incomplete) 2022-06-22 23:59:56 +03:00
Dmitry Stogov
082bcf89c9 Use ir_ctx.fixed_regset to limit available registers 2022-06-21 16:13:14 +03:00
Dmitry Stogov
00e92483bc Fix compilation warnings 2022-06-21 11:41:59 +03:00
Dmitry Stogov
5ef1e97261 Better support for unreachable basic blocks 2022-06-20 16:34:44 +03:00
Dmitry Stogov
5cafe50d36 Initial support for PHP 2022-06-10 00:16:29 +03:00
Dmitry Stogov
3212cd5bd2 Fix compilation warnings 2022-06-07 14:43:35 +03:00
Dmitry Stogov
91bddc09ed Cleanup & unification 2022-06-01 00:34:45 +03:00
Dmitry Stogov
00c300fc9f Start Aarch64 back-end 2022-05-31 11:22:31 +03:00
Dmitry Stogov
41f3e43cf7 cleanup 2022-05-27 13:18:04 +03:00
Dmitry Stogov
3e1816a71f Fix register allocation for ABS_INT 2022-05-27 00:11:31 +03:00
Dmitry Stogov
2840227291 Fixed assertion 2022-05-26 21:44:36 +03:00
Dmitry Stogov
4974c301bc Fix code generation for preserved registers and dessa moves 2022-05-26 18:08:39 +03:00
Dmitry Stogov
e28a3c801e Fix retutn FP numbers for 32-bit x86 back-end 2022-05-26 11:58:51 +03:00
Dmitry Stogov
9215162833 Ger rid of ir_ctx.bb_num and double neaning of ir_ctx.prev_insn_len 2022-05-25 11:58:35 +03:00
Dmitry Stogov
740cac8e2f Move ir_ctx.unused_live_ranges to local variable 2022-05-25 10:57:21 +03:00
Dmitry Stogov
c9bb858e50 Fuse loads without register allocation when this makes sense. 
Make oarameters passed through stack to reuse the same stack slot for spilling.
 2022-05-19 10:53:08 +03:00
Dmitry Stogov
1af065058b Use better name 2022-05-19 09:15:45 +03:00
Dmitry Stogov
e9e214d7d9 Remove special support for "_spill_" variable 2022-05-18 17:32:32 +03:00
Dmitry Stogov
0189eb28d0 Use a kind of "Buddy Allocaor" to pack spill slots of different sizes 2022-05-17 00:17:59 +03:00
Dmitry Stogov
6fb5380906 Take into account spill slot size and alignment 2022-05-16 22:16:29 +03:00
Dmitry Stogov
5f529a9d67 Hint propagation 2022-05-16 11:53:10 +03:00
Dmitry Stogov
e8dd422167 Cleanup "top" usage 2022-05-16 10:19:30 +03:00
Dmitry Stogov
e4e3336b2b Take into account registers used to pass constants 2022-05-13 15:26:11 +03:00
Dmitry Stogov
896ddb9e77 Flexable scratch register constraints (allow MUL %edx) 2022-05-13 15:10:15 +03:00
Dmitry Stogov
3dac541928 LSRA cleanup 2022-05-13 12:14:21 +03:00
Dmitry Stogov
4eaca331b9 Allow using debug_regset in RELEASE build 2022-05-13 09:22:31 +03:00
Dmitry Stogov
cd6eb1354a Renumber virtual registers 2022-05-13 01:15:24 +03:00
Dmitry Stogov
1f673ebfda Better temporary register usage for SSA deconstruction 2022-05-13 00:32:37 +03:00
Dmitry Stogov
386b140265 Refactor Linear Scan Register Allocator to use linked lists instead of bitsets 
This fixes allocation of several temporary variables for single instruction
 2022-05-12 17:43:08 +03:00
Dmitry Stogov
1028d7d330 Fix reading behind array range 2022-05-12 11:04:20 +03:00
Dmitry Stogov
c2d224148b Use prefered register if possible 2022-05-11 21:10:35 +03:00
Dmitry Stogov
69b5a852e5 Make DESSA API use "ir_ref" instead of "virtual register number" 
(0 - is still a temporary register)
 2022-05-06 16:19:57 +03:00
Dmitry Stogov
9f1ca6b82c Add IR_LIVE_INTERVAL_TEMP and IR_LIVE_INTERVAL_VAR flags 2022-05-06 09:23:14 +03:00
Dmitry Stogov
dd5a3a3b72 Add flexible support for temporary registers. 
Get rid of hardcoded temporary registers (incomplete)
 2022-05-05 22:35:39 +03:00
Dmitry Stogov
1130c256ae Find optimal split position 2022-05-04 11:59:35 +03:00
Dmitry Stogov
4f294109e8 Result of PARAM may be stored into a spill slot without register 2022-05-04 09:50:23 +03:00
Dmitry Stogov
1b156c49e8 Use "hint" regiser only if it's not disabled by "--debug-regset" 2022-05-04 09:08:23 +03:00
Dmitry Stogov
27540fd43a Use optimal split position (incompete) 2022-04-29 19:24:15 +03:00
Dmitry Stogov
b3c61507a4 Fixed possible incorrect splitting 2022-04-29 18:50:57 +03:00
Dmitry Stogov
102b367d64 cleanup 2022-04-29 15:24:41 +03:00
Dmitry Stogov
f5f9614854 cleanup 2022-04-29 14:19:53 +03:00
Dmitry Stogov
23945c4bdc Better debug logging 2022-04-29 12:14:26 +03:00
Dmitry Stogov
2e3ba321f8 Swap UsePos flags and prefer to reload registers that SHOULD be in a CPU register 2022-04-29 03:39:32 +03:00
Dmitry Stogov
3e6f84eef4 Add "must be in reg" constraint 2022-04-28 14:48:43 +03:00
Dmitry Stogov
ea46798aeb Fix live interval splitting and second chance binpacking (it seems to work, but may be icomplete) 2022-04-28 13:09:55 +03:00
Dmitry Stogov
acffada3b1 Fix interval processing order 2022-04-28 10:27:01 +03:00
Dmitry Stogov
fffc0ad2ef Delay spill slot allocation 2022-04-28 10:16:02 +03:00
Dmitry Stogov
53532fcb39 Select better register 2022-04-28 01:25:10 +03:00
Dmitry Stogov
5b7a7decd0 Fix splitting of use positions 2022-04-28 00:12:01 +03:00
Dmitry Stogov
9287830a77 Process remaining splits after all unhandled intervals 2022-04-27 23:31:20 +03:00
Dmitry Stogov
59b63cbb91 Sort oputput UsePos after inputs 2022-04-27 21:24:51 +03:00
Dmitry Stogov
7f8f186abd Fix the way as linera-scan walks through splitted intervals 2022-04-27 18:18:53 +03:00
Dmitry Stogov
6e77f886cb LSRA tweaks 2022-04-27 15:02:51 +03:00
Dmitry Stogov
2b9e793b4e Add debug options 2022-04-27 14:47:52 +03:00
Dmitry Stogov
c89246f35a Replace asserts with checks 2022-04-27 01:34:29 +03:00
Dmitry Stogov
329e1f5a44 Fix splitting (incomplete) 2022-04-27 01:04:03 +03:00
Dmitry Stogov
beaa2744e1 Keep fixed live intervals after coalescing 2022-04-26 21:16:22 +03:00
Dmitry Stogov
1370629b47 Fixed interval sorting 2022-04-26 11:51:48 +03:00
Dmitry Stogov
6548818887 Improve interval splitting (incomplete) 2022-04-26 00:54:07 +03:00
Dmitry Stogov
648d7084bc Fix intrval reconstruction after operand swapping 2022-04-25 21:00:01 +03:00
Dmitry Stogov
034ef95e07 Allow memory update instructions (without loading into register) 2022-04-22 01:40:10 +03:00
Dmitry Stogov
84b2bac02c Add more tests 2022-04-22 00:11:34 +03:00
Dmitry Stogov
c36efda8a5 Improve register allocation for commutative instructions 
- swap operands f this make sense
- fix coalescing bug
 2022-04-21 16:38:18 +03:00
Dmitry Stogov
20c9f2e92a Add comment 2022-04-20 19:30:28 +03:00
Dmitry Stogov
ffdb53821d Refactor constraint model 
Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE.
Hardware constraints are modeled conectiong live intervals and fixed
intervals to different sub-positions.
 2022-04-20 18:53:15 +03:00
Dmitry Stogov
6b60d8fba9 Code generation for VLOAD and VSTORE 2022-04-19 22:35:29 +03:00
Dmitry Stogov
879c4e75f5 Update vreg hints when compacting 2022-04-15 16:14:42 +03:00
Dmitry Stogov
0922b7cd7f Add vreg hints 2022-04-15 16:02:23 +03:00
Dmitry Stogov
9f24f34aca Cleanup 2022-04-15 14:46:03 +03:00
Dmitry Stogov
3cb707522f Allocate scratch (caller-saved) registers first 2022-04-15 14:22:35 +03:00
Dmitry Stogov
2c2f2dabab Better use placement 2022-04-15 00:35:02 +03:00
Dmitry Stogov
3f6a6aa3ea Better CPU constraint model and initial support for live interval splitting (incomplete) 2022-04-14 22:40:13 +03:00
Dmitry Stogov
58c80c48e0 Create fixed interval for a temporary register used for DESSA moves 2022-04-12 16:09:53 +03:00
Dmitry Stogov
14f4fdf29d Added few more basic x86_64 tests 2022-04-08 00:29:49 +03:00
Dmitry Stogov
e2601c8e06 Improve JIT support for IR_CALL 2022-04-07 23:41:38 +03:00
Dmitry Stogov
02863d7dc9 Initial JIT support for IR_CALL 2022-04-07 18:08:06 +03:00
Dmitry Stogov
23bd7fb272 Add hints and fixed intrvals for parameters 2022-04-07 14:18:59 +03:00
Dmitry Stogov
5b34386f62 Register Allocator suppor for fixed registers, use positions and register hints (incomplete). 2022-04-07 11:11:57 +03:00
Dmitry Stogov
2937993190 Initial import 2022-04-06 00:19:23 +03:00