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962 Commits 2 Branches 0 Tags 3.2 MiB
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396 Commits

Author SHA1 Message Date
Dmitry Stogov
90b6f34db2 Add FRAME_ADDR node 2023-11-16 01:59:26 +03:00
Dmitry Stogov
091907f4a4 Fixed typo 2023-10-25 08:40:26 +03:00
Dmitry Stogov
6edb011548 Fixed code generation for unordered floating point comparison 
- Fixed COND on AArch64
- Fixed SYM support on AArch64
 2023-10-24 10:22:04 +03:00
Dmitry Stogov
49316643e7 Initial support for modules (incomplete) 2023-10-20 17:44:45 +03:00
Dmitry Stogov
9b1ce974cb Improve loader interface (incomplete) 2023-10-20 01:09:46 +03:00
Dmitry Stogov
613fca0327 Implemented code generation for COND (not optimized) 2023-10-13 20:50:23 +03:00
Dmitry Stogov
62b6ddf149 Fixed code generation for rare address mode 2023-10-13 13:29:59 +03:00
Dmitry Stogov
d641c7949a Support for unordered FP comparison (x86[_64] yet, needs tests) 2023-10-13 12:52:56 +03:00
Dmitry Stogov
1b978f67ce Fix codegeneration for negative 8 and 16-bit immediate values 2023-10-13 11:15:19 +03:00
Javier Eguiluz
2f4f8504d4
Fix some typos (#51) 2023-10-03 08:34:02 +03:00
Dmitry Stogov
51a37f159b Initial implementation of LLVM export 2023-09-28 20:44:45 +03:00
Dmitry Stogov
09829a9e69 Fixed x86_64 calling convention for vararg functions 
%al is used as a hidden register to specify the number of passed vector registers
 2023-09-27 10:23:34 +03:00
Dmitry Stogov
a2f8452b3d Fixed code generation for MOD 2023-09-18 13:10:19 +03:00
Dmitry Stogov
8977307f4e Improve error handling 2023-09-14 20:15:30 +03:00
Dmitry Stogov
83de21eccd Fixed argument sign/zero extension 2023-09-12 20:47:45 +03:00
Dmitry Stogov
5953d17f5f Don't miss spill loads when the register valuses are reused 2023-09-12 16:12:12 +03:00
Dmitry Stogov
f44e897bb2 Set IR_TLS.op3 to IR_NULL, if unused 2023-09-04 16:39:21 +03:00
Dmitry Stogov
02afd0a89f Fixed code generation for IR_MUL/DIV/MOD_INT with result in a spill slot 2023-09-01 12:18:05 +03:00
Dmitry Stogov
316bc37e8b Support for MACOS TLS 2023-09-01 08:49:05 +03:00
Dmitry Stogov
dd2ecad299 Allow reuse of spill slots for objecs of smaller size 2023-08-02 13:20:13 +03:00
Dmitry Stogov
1d49fe6cc4 Reduce cost of disabled IR_ASSERT() 2023-07-27 11:16:00 +03:00
Dmitry Stogov
f6cf9140da Update ir_insn.inputs_count and use it after ir_build_def_use_lists() 2023-07-06 01:15:08 +03:00
Dmitry Stogov
ce2d6ceba6 Fixed non-boolean constant GUARD condition checks 2023-06-29 23:49:20 +03:00
Dmitry Stogov
7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
 2023-06-29 12:42:44 +03:00
Dmitry Stogov
9cec28c188 Fixed compilation warnings 2023-06-22 14:50:14 +03:00
Dmitry Stogov
85beed7901 Fixed incorrect oredering of moves during de-SSA 
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
 2023-06-22 12:07:19 +03:00
Dmitry Stogov
99bcde9e1e Cleanup spill related code 2023-06-21 23:20:58 +03:00
Dmitry Stogov
d67c212916 Separate codegen info output into ir_dump_codegen() 2023-06-21 22:36:36 +03:00
Dmitry Stogov
ebaefd376a Fix stack frame and assign all spill slots before code genearatin 2023-06-21 19:04:22 +03:00
Dmitry Stogov
4124ef5150 Allow printing IR annotated with register-allocation, spill-code-placement, de-SSA and code-generation information 2023-06-21 13:28:15 +03:00
Dmitry Stogov
25656607ba Variabls with a register constraint may be loaed/stored directly from/to a spill slot (without an additional register) 2023-06-21 01:14:31 +03:00
Dmitry Stogov
ffac404552 Fix impossible load fusion 2023-06-20 12:14:52 +03:00
Dmitry Stogov
b37d4e0443 Allow usage of CPU stack slots for deoptimization 2023-06-16 02:14:02 +03:00
Dmitry Stogov
6a98514bdc Move stack size related metricks to ir_ctx 2023-06-15 19:28:54 +03:00
Dmitry Stogov
311267714e Use macros insted of bit ops 2023-06-14 20:23:32 +03:00
Dmitry Stogov
defd58cec3 Store proper %sp register value 2023-06-13 18:22:21 +03:00
Dmitry Stogov
257bdff21a Fix compilation warnings 2023-06-09 10:58:58 +03:00
Dmitry Stogov
b8be0b9dd9 Avoid loading of stack parameter to register if this is not necessary 2023-06-09 00:35:15 +03:00
Dmitry Stogov
ae4daf223e Replace assertion with a non-fatal error 2023-06-07 18:39:51 +03:00
Dmitry Stogov
3de6c5126a Avoid code generation for useless loads and stores 2023-06-07 14:43:16 +03:00
Dmitry Stogov
18bdfb4203 Bettter code scheduling 2023-06-06 23:55:15 +03:00
Dmitry Stogov
186dc6b0a6 Fixed GH issue #33: IR program failed to compile with "-O0" "-S" options 2023-06-05 18:22:12 +03:00
Dmitry Stogov
b5bb5f869a Fixed GH Issue #34 (Simple if-else IR program compile failure) 2023-06-05 14:21:03 +03:00
Dmitry Stogov
87f2fc7f69 Fixed typo 2023-05-29 15:52:17 +03:00
Dmitry Stogov
20b9a7513c Fixed missing label 2023-05-26 09:08:57 +03:00
Dmitry Stogov
2a80257535 Support for more C escape sequences 2023-05-22 19:51:19 +03:00
Dmitry Stogov
d3640495a2 Ceanup ir_compute_live_ranges() implementation 2023-05-19 12:34:54 +03:00
Dmitry Stogov
5c2023fd7f Avoid live range constrction for VARs 2023-05-18 21:00:57 +03:00
Dmitry Stogov
477dbf7d76 Avoid live range constrction for RLOAD with fixed registers 2023-05-18 13:37:12 +03:00
Dmitry Stogov
c9fa8dfebd Fixed SSA deconstruction 
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
 2023-05-17 22:37:45 +03:00