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6 Commits

Author SHA1 Message Date
Dmitry Stogov
4f9724a7fb Fix tests 2023-10-13 21:04:38 +03:00
Dmitry Stogov
66e9693019 Fix tests 2023-10-13 20:57:42 +03:00
Dmitry Stogov
613fca0327 Implemented code generation for COND (not optimized) 2023-10-13 20:50:23 +03:00
Dmitry Stogov
7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
 2023-06-29 12:42:44 +03:00
Dmitry Stogov
c89a038fd3 Fix tests with capstone 5 
Different versions of capstone may disassemble MOVD/MOVQ differentrly
 2023-03-02 17:54:50 +03:00
Dmitry Stogov
ebdeba9fff Add simple tests for Windows-x86_64 
conv_004.irt and conv_010.irt fail with capstone 5 because of changes in movd/movq
 2023-03-02 00:55:20 +03:00