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abs_001.irt
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Implement ABS and NEG
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2022-04-21 00:31:28 +03:00 |
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abs_002.irt
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Implement ABS and NEG
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2022-04-21 00:31:28 +03:00 |
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abs_003.irt
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Implement ABS and NEG
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2022-04-21 00:31:28 +03:00 |
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add_001.irt
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Use LEA for 32-bit integers
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2022-04-14 18:11:43 +03:00 |
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add_002.irt
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Use LEA for 32-bit integers
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2022-04-14 18:11:43 +03:00 |
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add_003.irt
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Use LEA for 32-bit integers
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2022-04-14 18:11:43 +03:00 |
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add_004.irt
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Use LEA for 32-bit integers
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2022-04-14 18:11:43 +03:00 |
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add_005.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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add_006.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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add_007.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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add_008.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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add_009.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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add_010.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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add_011.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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add_012.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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add_ov_001.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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add_ov_002.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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add_ov_003.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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add_ov_004.irt
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Reorder blocks according to branch probability
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2022-05-24 12:47:39 +03:00 |
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alloca_001.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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alloca_002.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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bswap_001.irt
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Added tests for unary integer instructions
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2022-04-08 16:40:28 +03:00 |
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conv_001.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_002.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_003.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_004.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_005.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_006.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_007.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_008.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_009.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_010.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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conv_011.irt
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Implement code generation for type conversion instructions
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2022-05-20 13:07:41 +03:00 |
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div_001.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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div_002.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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div_003.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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div_004.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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div_005.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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eq_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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eq_002.irt
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Added more x86_64 tests for integer comparison
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2022-04-08 10:05:42 +03:00 |
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eq_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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eq_004.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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eq_005.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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ge_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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ge_002.irt
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Added more x86_64 tests for integer comparison
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2022-04-08 10:05:42 +03:00 |
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ge_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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ge_004.irt
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Support for unordered floating point comparison
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2022-04-08 15:29:05 +03:00 |
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ge_005.irt
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Support for unordered floating point comparison
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2022-04-08 15:29:05 +03:00 |
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gt_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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gt_002.irt
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Added more x86_64 tests for integer comparison
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2022-04-08 10:05:42 +03:00 |
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gt_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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gt_004.irt
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Support for unordered floating point comparison
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2022-04-08 15:29:05 +03:00 |
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gt_005.irt
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Support for unordered floating point comparison
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2022-04-08 15:29:05 +03:00 |
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le_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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le_002.irt
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Added more x86_64 tests for integer comparison
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2022-04-08 10:05:42 +03:00 |
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le_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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le_004.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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le_005.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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lt_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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lt_002.irt
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Added more x86_64 tests for integer comparison
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2022-04-08 10:05:42 +03:00 |
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lt_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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lt_004.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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lt_005.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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min_001.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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min_002.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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min_003.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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min_004.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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min_005.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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min_006.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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mod_001.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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mod_002.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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mod_003.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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mod_004.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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mod_005.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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mul_001.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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mul_002.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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mul_003.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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mul_004.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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mul_005.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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mul_006.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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mul_ov_001.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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mul_ov_002.irt
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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ne_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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ne_002.irt
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Added more x86_64 tests for integer comparison
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2022-04-08 10:05:42 +03:00 |
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ne_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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ne_004.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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ne_005.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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neg_001.irt
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Added tests for unary integer instructions
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2022-04-08 16:40:28 +03:00 |
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neg_002.irt
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Implement ABS and NEG
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2022-04-21 00:31:28 +03:00 |
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neg_003.irt
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Implement ABS and NEG
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2022-04-21 00:31:28 +03:00 |
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not_001.irt
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Support for more instruction in C backend and BOOL_NOT in x86_86
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2022-04-08 19:02:11 +03:00 |
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not_002.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_001.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_002.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_003.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_004.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_005.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_006.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_007.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_008.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_009.irt
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Better use placement
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2022-04-15 00:35:02 +03:00 |
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ra_010.irt
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Flexable scratch register constraints (allow MUL %edx)
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2022-05-13 15:10:15 +03:00 |
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ra_011.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_012.irt
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Better CPU constraint model and initial support for live interval splitting (incomplete)
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2022-04-14 22:40:13 +03:00 |
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ra_013.irt
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Allocate scratch (caller-saved) registers first
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2022-04-15 14:22:35 +03:00 |
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ra_014.irt
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Clenaup (remove unnecessary SHIFT case)
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2022-05-16 14:36:27 +03:00 |
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ra_015.irt
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Clenaup (remove unnecessary SHIFT case)
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2022-05-16 14:36:27 +03:00 |
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shl_001.irt
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Clenaup (remove unnecessary SHIFT case)
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2022-05-16 14:36:27 +03:00 |
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shl_002.irt
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Added few more basic x86_64 tests
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2022-04-08 00:29:49 +03:00 |
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shl_003.irt
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Clenaup (remove unnecessary SHIFT case)
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2022-05-16 14:36:27 +03:00 |
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shl_004.irt
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Clenaup (remove unnecessary SHIFT case)
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2022-05-16 14:36:27 +03:00 |
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sub_001.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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sub_002.irt
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Use LEA for 32-bit integers
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2022-04-14 18:11:43 +03:00 |
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sub_003.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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sub_004.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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sub_005.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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sub_006.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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sub_007.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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sub_008.irt
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ws
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2022-04-07 23:31:03 +03:00 |
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sub_009.irt
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Add tests for 64-bit constants
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2022-05-04 15:37:07 +03:00 |
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sub_010.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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sub_011.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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sub_012.irt
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Add flexible support for temporary registers.
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2022-05-05 22:35:39 +03:00 |
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uge_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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uge_002.irt
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Added more x86_64 tests for integer comparison
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2022-04-08 10:05:42 +03:00 |
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uge_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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ugt_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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ugt_002.irt
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Added more x86_64 tests for integer comparison
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2022-04-08 10:05:42 +03:00 |
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ugt_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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ule_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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ule_002.irt
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Added more x86_64 tests for integer comparison
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2022-04-08 10:05:42 +03:00 |
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ule_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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ult_001.irt
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Added x86_64 tests for integer comparison
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2022-04-08 00:59:45 +03:00 |
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ult_002.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
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ult_003.irt
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x86_64: Optimize integer comparison with zero
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2022-04-08 10:49:22 +03:00 |
