ir/tests
2023-10-11 22:55:25 +03:00
..
aarch64 Remove useless "AVX" tests for AArch64 2023-04-18 10:14:59 +03:00
bugs Fixed GH issue #33: IR program failed to compile with "-O0" "-S" options 2023-06-05 18:22:12 +03:00
c Initial implementation of LLVM export 2023-09-28 20:44:45 +03:00
debug Introduce API to load modules 2023-10-11 22:55:25 +03:00
debug.aarch64 Introduce API to load modules 2023-10-11 22:55:25 +03:00
debug.Windows-x86_64 Introduce API to load modules 2023-10-11 22:55:25 +03:00
debug.x86 Introduce API to load modules 2023-10-11 22:55:25 +03:00
folding Add more folding rules 2023-03-29 14:07:31 +03:00
llvm LLVM support for fastcall and vararg 2023-09-29 11:30:53 +03:00
Windows-x86_64 More accurate spill loads optimization for instructions that reuse op1 register for result 2023-06-29 12:42:44 +03:00
x86 Avoid MOVD/MOVQ disassemble mismatch with old/new capstone versions 2023-09-19 16:30:09 +03:00
x86_64 Avoid MOVD/MOVQ disassemble mismatch with old/new capstone versions 2023-09-19 16:30:09 +03:00
001.irt Initial import 2022-04-06 00:19:23 +03:00
002.irt typo 2022-08-23 17:02:34 +03:00
003.irt Initial import 2022-04-06 00:19:23 +03:00
004.irt Fix some typos (#51) 2023-10-03 08:34:02 +03:00
005.irt Fix some typos (#51) 2023-10-03 08:34:02 +03:00
006.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
007.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
008.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
009.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
010.irt Added type compatibility assertion and fixed mistakes in tests 2023-05-22 20:48:07 +03:00
011.irt Initial import 2022-04-06 00:19:23 +03:00
012.irt Initial import 2022-04-06 00:19:23 +03:00
013.irt Added type compatibility assertion and fixed mistakes in tests 2023-05-22 20:48:07 +03:00
014.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
015.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
016.irt Added type compatibility assertion and fixed mistakes in tests 2023-05-22 20:48:07 +03:00
017.irt Initial import 2022-04-06 00:19:23 +03:00
018.irt Initial import 2022-04-06 00:19:23 +03:00
019.irt Added type compatibility assertion and fixed mistakes in tests 2023-05-22 20:48:07 +03:00
020.irt Reimplement JMP optimization 2022-08-30 23:15:20 +03:00
021.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
022.irt Fix some typos (#51) 2023-10-03 08:34:02 +03:00
023.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
024.irt Fix some typos (#51) 2023-10-03 08:34:02 +03:00
025.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
dead_load_001.irt Extend SCCP to perform Dead Load Elimination 2022-11-08 15:39:00 +03:00
dead_load_002.irt Extend SCCP to perform Dead Load Elimination 2022-11-08 15:39:00 +03:00
dead_load_003.irt Extend SCCP to perform Dead Load Elimination 2022-11-08 15:39:00 +03:00
fibi_min.irt Fixed x86_64 calling convention for vararg functions 2023-09-27 10:23:34 +03:00
fp_const.irt Fixed x86_64 calling convention for vararg functions 2023-09-27 10:23:34 +03:00