danog/ir
1
0
Fork 0
mirror of https://github.com/danog/ir.git synced 2025-01-22 05:31:32 +01:00
Code Issues Packages Projects Releases Wiki Activity
ir/tests/debug.x86
History
Dmitry Stogov 7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
2023-06-29 12:42:44 +03:00
..
args_001.irt
Improve x86 code generation for passing address of label to stack
2023-03-29 15:48:41 +03:00
args_002.irt
Improve x86 code generation for passing address of label to stack
2023-03-29 15:48:41 +03:00
call2.irt
Avoid loading of stack parameter to register if this is not necessary
2023-06-09 00:35:15 +03:00
call3.irt
Avoid loading of stack parameter to register if this is not necessary
2023-06-09 00:35:15 +03:00
call_002.irt
Improve x86 code generation for passing address of label to stack
2023-03-29 15:48:41 +03:00
call_alloca.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
call_vaddr.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
call-O0.irt
Improve x86 code generation for passing address of label to stack
2023-03-29 15:48:41 +03:00
call.irt
Improve x86 code generation for passing address of label to stack
2023-03-29 15:48:41 +03:00
combo_001.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
combo_002.irt
Added type compatibility assertion and fixed mistakes in tests
2023-05-22 20:48:07 +03:00
combo_003.irt
Added type compatibility assertion and fixed mistakes in tests
2023-05-22 20:48:07 +03:00
combo_004.irt
Fixed mistakes in GCM algorithm
2023-05-29 17:02:50 +03:00
dce_001.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
dessa_001.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
dessa_002.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
dessa_003.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
fig-O0.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
fig.irt
Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator"
2023-06-28 22:00:50 +03:00
ijmp_001.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
lea_001.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
loop_001.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
loop_002.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
memop_001.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
memop_002.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
memop_003.irt
Improve load fusion, register allocateion and code selection for ADD
2023-02-21 22:55:47 +03:00
memop_004.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
memop_005.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
memop_006.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
memop_007.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
memop_008.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
params_001.irt
Avoid loading of stack parameter to register if this is not necessary
2023-06-09 00:35:15 +03:00
params_002.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
params_003.irt
Improve x86 code generation for passing address of label to stack
2023-03-29 15:48:41 +03:00
regset-fib2.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
regset-fib.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
regset-fibi.irt
Fixed SSA deconstruction
2023-05-17 22:37:45 +03:00
regset-test.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
sccp_001.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
sccp_002.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
swap_001.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
swap_002.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
switch_001.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
switch_002.irt
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
tailcall_001.irt
Remove data dependency between TAILCALL and UNREACHABLE
2023-04-13 02:41:28 +03:00
tailcall_002.irt
Remove data dependency between TAILCALL and UNREACHABLE
2023-04-13 02:41:28 +03:00
test_mem.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test_var-O0.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test_var.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test-mavx.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test-O0.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00