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args_001.irt
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Add support for Windows-64 ABI ("home space")
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2023-03-02 13:27:01 +03:00 |
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args_002.irt
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Fix register clobbering during argument passing
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2022-12-26 18:27:53 +03:00 |
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call2.irt
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Improve load fusion, register allocateion and code selection for ADD
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2023-02-21 22:55:47 +03:00 |
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call3.irt
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Improve load fusion, register allocateion and code selection for ADD
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2023-02-21 22:55:47 +03:00 |
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call_002.irt
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Extend disassembler to support .rodata section and IP relative data labels
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2022-05-26 01:17:02 +03:00 |
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call_003.irt
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Improve parallel copy algorithm to support move of single source into multiple destinations
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2023-04-26 10:56:55 +03:00 |
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call_alloca.irt
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Fuse address calculation into LOAD/STORE
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2022-08-24 16:11:04 +03:00 |
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call_vaddr.irt
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Fuse address calculation into LOAD/STORE
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2022-08-24 16:11:04 +03:00 |
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call-O0.irt
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Extend disassembler to support .rodata section and IP relative data labels
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2022-05-26 01:17:02 +03:00 |
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call.irt
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Extend disassembler to support .rodata section and IP relative data labels
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2022-05-26 01:17:02 +03:00 |
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combo_001.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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combo_002.irt
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Added type compatibility assertion and fixed mistakes in tests
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2023-05-22 20:48:07 +03:00 |
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combo_003.irt
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Added type compatibility assertion and fixed mistakes in tests
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2023-05-22 20:48:07 +03:00 |
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combo_004.irt
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Fixed mistakes in GCM algorithm
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2023-05-29 17:02:50 +03:00 |
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dce_001.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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dessa_001.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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dessa_002.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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dessa_003.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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fig-O0.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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fig.irt
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Fixed incorrect oredering of moves during de-SSA
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2023-06-22 12:07:19 +03:00 |
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ijmp_001.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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lea_001.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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loop_001.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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loop_002.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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memop_001.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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memop_002.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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memop_003.irt
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Validate operand types
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2022-06-03 11:23:05 +03:00 |
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memop_004.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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memop_005.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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memop_006.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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memop_007.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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memop_008.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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memop_009.irt
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Fix impossible load fusion
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2023-06-20 12:14:52 +03:00 |
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memop_010.irt
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Fix impossible load fusion
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2023-06-20 12:14:52 +03:00 |
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params_001.irt
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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params_002.irt
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Better usage of the register hints
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2023-06-09 16:26:15 +03:00 |
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params_003.irt
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Avoid reservaton of temporary resiser for argument passing
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2023-04-26 12:16:05 +03:00 |
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ra_001.irt
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Improve load fusion, register allocateion and code selection for ADD
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2023-02-21 22:55:47 +03:00 |
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ra_002.irt
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Split assign_regs() loop into two versions (with and without spilling).
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2023-06-20 08:34:54 +03:00 |
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ra_003.irt
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Split assign_regs() loop into two versions (with and without spilling).
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2023-06-20 08:34:54 +03:00 |
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regset-fib2.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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regset-fib.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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regset-fibi.irt
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Fixed SSA deconstruction
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2023-05-17 22:37:45 +03:00 |
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regset-test.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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sccp_001.irt
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Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32")
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2023-02-17 18:11:13 +03:00 |
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sccp_002.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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swap_001.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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swap_002.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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switch_001.irt
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Fix buffer overflow
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2022-05-26 17:19:43 +03:00 |
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switch_002.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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switch_003.irt
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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tailcall_001.irt
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Remove data dependency between TAILCALL and UNREACHABLE
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2023-04-13 02:41:28 +03:00 |
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tailcall_002.irt
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Remove data dependency between TAILCALL and UNREACHABLE
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2023-04-13 02:41:28 +03:00 |
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test64.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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test_mem.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test_var-O0.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test_var.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test-mavx.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test-O0.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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