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ir/tests/debug.Windows-x86_64
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Dmitry Stogov 7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
2023-06-29 12:42:44 +03:00
..
args_001.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
args_002.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
call2.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
call3.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
call_002.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
call_alloca.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
call_vaddr.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
call-O0.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
call.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
combo_001.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
combo_002.irt
Added type compatibility assertion and fixed mistakes in tests
2023-05-22 20:48:07 +03:00
combo_003.irt
Added type compatibility assertion and fixed mistakes in tests
2023-05-22 20:48:07 +03:00
combo_004.irt
Fixed mistakes in GCM algorithm
2023-05-29 17:02:50 +03:00
dce_001.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
dessa_001.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
dessa_002.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
dessa_003.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
fig-O0.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
fig.irt
Fixed incorrect oredering of moves during de-SSA
2023-06-22 12:07:19 +03:00
ijmp_001.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
lea_001.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
loop_001.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
loop_002.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
memop_001.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
memop_002.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
memop_003.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
memop_004.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
memop_005.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
memop_006.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
memop_007.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
memop_008.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
params_001.irt
Fix test
2023-06-09 10:58:49 +03:00
params_002.irt
Fixed tests
2023-06-09 16:29:38 +03:00
params_003.irt
Fixed test
2023-04-26 14:24:43 +03:00
ra_001.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
regset-fib2.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
regset-fib.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
regset-fibi.irt
Fix Win64 tests
2023-05-17 22:49:26 +03:00
regset-test.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
sccp_001.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
sccp_002.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
swap_001.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
swap_002.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
switch_001.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
switch_002.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
switch_003.irt
Add complex WIN64 tests
2023-03-02 17:57:26 +03:00
tailcall_001.irt
Remove data dependency between TAILCALL and UNREACHABLE
2023-04-13 02:41:28 +03:00
tailcall_002.irt
Remove data dependency between TAILCALL and UNREACHABLE
2023-04-13 02:41:28 +03:00
test64.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
test_mem.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test_var-O0.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test_var.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test-mavx.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test-O0.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00