Dmitry Stogov 7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result ...

This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]

2023-06-29 12:42:44 +03:00

..

aarch64

Remove useless "AVX" tests for AArch64

2023-04-18 10:14:59 +03:00

bugs

Fixed GH issue #33: IR program failed to compile with "-O0" "-S" options

2023-06-05 18:22:12 +03:00

c

Added test

2023-05-29 17:11:26 +03:00

debug

More accurate spill loads optimization for instructions that reuse op1 register for result

2023-06-29 12:42:44 +03:00

debug.aarch64

Improve live interval splitting and eliminate more redundand spill loads

2023-06-27 11:29:26 +03:00

debug.Windows-x86_64

More accurate spill loads optimization for instructions that reuse op1 register for result

2023-06-29 12:42:44 +03:00

debug.x86

More accurate spill loads optimization for instructions that reuse op1 register for result

2023-06-29 12:42:44 +03:00

folding

Add more folding rules

2023-03-29 14:07:31 +03:00

Windows-x86_64

More accurate spill loads optimization for instructions that reuse op1 register for result

2023-06-29 12:42:44 +03:00

x86

More accurate spill loads optimization for instructions that reuse op1 register for result

2023-06-29 12:42:44 +03:00

x86_64

More accurate spill loads optimization for instructions that reuse op1 register for result

2023-06-29 12:42:44 +03:00

001.irt

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002.irt

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003.irt

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004.irt

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005.irt

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006.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

007.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

008.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

009.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

010.irt

Added type compatibility assertion and fixed mistakes in tests

2023-05-22 20:48:07 +03:00

011.irt

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012.irt

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013.irt

Added type compatibility assertion and fixed mistakes in tests

2023-05-22 20:48:07 +03:00

014.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

015.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

016.irt

Added type compatibility assertion and fixed mistakes in tests

2023-05-22 20:48:07 +03:00

017.irt

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018.irt

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019.irt

Added type compatibility assertion and fixed mistakes in tests

2023-05-22 20:48:07 +03:00

020.irt

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021.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

022.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

023.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

024.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

025.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

dead_load_001.irt

Extend SCCP to perform Dead Load Elimination

2022-11-08 15:39:00 +03:00

dead_load_002.irt

Extend SCCP to perform Dead Load Elimination

2022-11-08 15:39:00 +03:00

dead_load_003.irt

Extend SCCP to perform Dead Load Elimination

2022-11-08 15:39:00 +03:00

fibi_min.irt

Add test

2023-03-22 22:09:25 +03:00