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283 lines
9.6 KiB
Markdown
283 lines
9.6 KiB
Markdown
# IR - Lightweight JIT Compilation Framework
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The main task of this framework is transformation of the IR (Intermediate
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Representation) into an optimized in-memory target machine code, that may
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be directly executed.
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This is not a stable finished product yet. It’s used as a base for development
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of the next generation JIT compiler for PHP-9. There are a lot of required
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things are not implemented yet.
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## IR - Intermediate Representation
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The Framework uses single Medium level Intermediate Representation during all
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phases of optimization, register allocation and code generation. It is inspired
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by Sea-Of-Nodes introduced by Cliff Click [1]. Sea-Of-Nodes is used in Java
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HotSpot Server Compiler, V8 TurboFan JavaScript Compiler, Java Graal
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Compiler...
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This representation unifies data and control dependencies into a single graph,
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where each instruction represented as a Node and each dependency as an Edge
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between Nodes. There are no classical CFG (Control Flow Graph) with Basic
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Blocks. Instead, IR uses special Control Nodes that start and finish some
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code Regions. The data part of the IR is very similar to SSA (Static Single
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Assignment) form. Each variable may be assigned only once, but except to SSA,
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in our IR, we don’t have any variables, their versions and name. Everything
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is represented by computation Nodes and Edges between them. Of course, we
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have special PHI Node that represents the Phi() function.
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Despite, our IR is graph based, internally, it’s represented as a plain
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two-way grow-able array of Nodes. Dependency Edge are represented as indexes
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of the other Node. This physical representation is almost completely repeats
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the LuaJIT IR designed by Mike Pall [3].
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## IR Generation
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TODO...
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## IR Optimization
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In comparison to classical optimizing compilers (like GCC and LLVM), IR
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Framework uses very short optimization pipeline. Together with compact IR
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representation, this makes it extremely fast and allows to generate quite
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good machine code in reasonable time.
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### Folding
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Folding is done on the fly, during IR generation. It performs a set of local
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transformations, but because of the graph nature of the IR where most data
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operations (like ADD) are “floating” (not “pinned” to Basic Block), the scope
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of transformations is not limited by Basic Block. It’s important to generate
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IR in a proper (Reverse Post) order, that would emit all Nodes before their
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first usage. (In case of different order the scope of the folding should be
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limited).
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Folding Engine performs Constants Folding, Copy Propagation, Algebraic
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Simplifications, Algebraic Re-Association and Common Sub-Expression
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Elimination. The simple and fast declarative implementation is borrowed from
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LuaJIT [3].
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### Sparse Conditional Constant Propagation
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This pass implements a classical algorithm originally designed by M. N. Wegman
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and F. K. Zadeck [4] for SSA form. Unification of data and control dependencies
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made its implementation even simple. Despite of constant propagation itself
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this pass also performs global Copy Propagation and re-applies the folding rules.
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At the end all the “dead” instructions (instructions that result are not used)
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are replaced with NOPs.
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### Global Code Motion
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Now we have to “fix” places of “floating” instructions. This pass builds CFG
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(Control Flow Graph) skeleton and then ”pin” each “floating” instruction to the
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best Basic Block. The algorithm is developed by Cliff Click [2].
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## Local Scheduling
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As the final IR transformation pass, we reorder instructions inside each Basic
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Block to satisfy the dependencies. Currently this is done by a simple
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topological sorting.
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## Target Instruction Selection
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This is the first target dependent step of compilation. It aims to combine
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instruction Nodes into tiles that allows better instruction fusion. For example
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``10 + a + b * 4`` may be calculated by a single x86 instruction
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``lea 10(%eax, %ebx, 4), %ecx``. The selection is done by a constrained tree
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pattern matching. The current implementation uses simple Max-Munch approach.
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(This may be replaced by a smarter BURS method).
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## Register Allocation
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CPU independent implementation of Linear Scan Register Allocation for SSA form
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with second chance bin-packing. [5] [6]
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## Machine Code Generations
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IR Framework implements X86_64, x86 and AAtch64 back-ends. The current
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implementation uses DynAsm [?]. (In the future, this should be replaced with
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a faster “binary” encoder). Code generator walks throw all instructions of each
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basic blocks and emits some code according to “rules” selected during
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instruction selection pass. It uses registers, selected by register allocator
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and inserts the necessary spill load/store and SSA deconstruction code.
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## Tooling
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- Ability to load and save IR in a textual form
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- Ability to visualize IR graph through graphviz dot.
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- Target CPU disassembler for generated code (uses libcapstone [?])
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- GDB/JIT interface to allow debugging of JIT-ed code
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- Linux perf interface to analyze the code performance
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## IR Example
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Let's try to generate code for the following function:
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```c
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int32_t mandelbrot(double x, double y)
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{
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double cr = y - 0.5;
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double ci = x;
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double zi = 0.0;
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double zr = 0.0;
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int i = 0;
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while(1) {
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i++;
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double temp = zr * zi;
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double zr2 = zr * zr;
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double zi2 = zi * zi;
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zr = zr2 - zi2 + cr;
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zi = temp + temp + ci;
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if (zi2 + zr2 > 16)
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return i;
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if (i > 1000)
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return 0;
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}
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}
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```
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This may be done through IR construction API by the following code:
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```c
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void gen_mandelbrot(ir_ctx *ctx)
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{
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ir_START();
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ir_ref x = ir_PARAM(IR_DOUBLE, "x", 1);
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ir_ref y = ir_PARAM(IR_DOUBLE, "y", 2);
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ir_ref cr = ir_SUB_D(y, ir_CONST_DOUBLE(0.5));
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ir_ref ci = ir_COPY_D(x);
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ir_ref zi = ir_COPY_D(ir_CONST_DOUBLE(0.0));
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ir_ref zr = ir_COPY_D(ir_CONST_DOUBLE(0.0));
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ir_ref i = ir_COPY_D(ir_CONST_I32(0));
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ir_ref loop = ir_LOOP_BEGIN(ir_END());
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ir_ref zi_1 = ir_PHI_2(zi, IR_UNUSED);
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ir_ref zr_1 = ir_PHI_2(zr, IR_UNUSED);
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ir_ref i_1 = ir_PHI_2(i, IR_UNUSED);
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ir_ref i_2 = ir_ADD_I32(i_1, ir_CONST_I32(1));
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ir_ref temp = ir_MUL_D(zr_1, zi_1);
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ir_ref zr2 = ir_MUL_D(zr_1, zr_1);
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ir_ref zi2 = ir_MUL_D(zi_1, zi_1);
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ir_ref zr_2 = ir_ADD_D(ir_SUB_D(zr2, zi2), cr);
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ir_ref zi_2 = ir_ADD_D(ir_ADD_D(temp, temp), ci);
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ir_ref if_1 = ir_IF(ir_GT(ir_ADD_D(zi2, zr2), ir_CONST_DOUBLE(16.0)));
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ir_IF_TRUE(if_1);
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ir_RETURN(i_2);
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ir_IF_FALSE(if_1);
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ir_ref if_2 = ir_IF(ir_GT(i_2, ir_CONST_I32(1000)));
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ir_IF_TRUE(if_2);
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ir_RETURN(ir_CONST_I32(0));
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ir_IF_FALSE(if_2);
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ir_ref loop_end = ir_LOOP_END(loop);
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/* close loop */
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ir_set_op2(ctx, loop, loop_end);
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ir_set_op3(ctx, zi_1, zi_2);
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ir_set_op3(ctx, zr_1, zr_2);
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ir_set_op3(ctx, i_1, i_2);
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}
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```
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The textual representation of the IR after system independent optimizations:
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```
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{
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uintptr_t c_1 = 0;
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bool c_2 = 0;
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bool c_3 = 1;
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double c_4 = 0.5;
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double c_5 = 0;
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int32_t c_6 = 0;
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int32_t c_7 = 1;
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double c_8 = 16;
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int32_t c_9 = 1000;
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l_1 = START(l_22);
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double d_2 = PARAM(l_1, "x", 1);
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double d_3 = PARAM(l_1, "y", 2);
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double d_4 = SUB(d_3, c_4);
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l_5 = END(l_1);
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l_6 = LOOP_BEGIN(l_5, l_29);
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double d_7 = PHI(l_6, c_5, d_28);
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double d_8 = PHI(l_6, c_5, d_26);
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int32_t d_9 = PHI(l_6, c_6, d_10);
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int32_t d_10 = ADD(d_9, c_7);
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double d_11 = MUL(d_8, d_8);
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double d_12 = MUL(d_7, d_7);
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double d_13 = ADD(d_12, d_11);
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bool d_14 = GT(d_13, c_8);
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l_15 = IF(l_6, d_14);
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l_16 = IF_TRUE(l_15);
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l_17 = RETURN(l_16, d_10);
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l_18 = IF_FALSE(l_15);
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bool d_19 = GT(d_10, c_9);
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l_20 = IF(l_18, d_19);
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l_21 = IF_TRUE(l_20);
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l_22 = RETURN(l_21, c_6, l_17);
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l_23 = IF_FALSE(l_20);
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double d_24 = MUL(d_7, d_8);
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double d_25 = SUB(d_11, d_12);
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double d_26 = ADD(d_25, d_4);
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double d_27 = ADD(d_24, d_24);
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double d_28 = ADD(d_27, d_2);
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l_29 = LOOP_END(l_23, l_6);
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}
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```
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The visualized graph:
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The final generated code:
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```asm
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test:
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subsd .L4(%rip), %xmm1
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xorpd %xmm3, %xmm3
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xorpd %xmm2, %xmm2
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xorl %eax, %eax
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.L1:
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leal 1(%rax), %eax
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movapd %xmm2, %xmm4
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mulsd %xmm2, %xmm4
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movapd %xmm3, %xmm5
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mulsd %xmm3, %xmm5
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movapd %xmm5, %xmm6
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addsd %xmm4, %xmm6
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ucomisd .L5(%rip), %xmm6
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ja .L2
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cmpl $0x3e8, %eax
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jg .L3
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mulsd %xmm2, %xmm3
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subsd %xmm5, %xmm4
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movapd %xmm4, %xmm2
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addsd %xmm1, %xmm2
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addsd %xmm3, %xmm3
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addsd %xmm0, %xmm3
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jmp .L1
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.L2:
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retq
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.L3:
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xorl %eax, %eax
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retq
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.rodata
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.L4:
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.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f
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.L5:
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.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40
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```
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## PHP JIT based on IR
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A new experimental JIT for PHP based on IR is developed at [php-ir](https://github.com/dstogov/php-src/tree/php-ir/ext/opcache/jit) branch.
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See [README-IR.md](https://github.com/dstogov/php-src/blob/php-ir/ext/opcache/jit/README-IR.md).
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## References
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1. C. Click, M. Paleczny. “A Simple Graph-Based Intermediate Representation” In ACM SIGPLAN Workshop on Intermediate Representations (IR '95), pages 35-49, Jan. 1995.
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2. C. Click. “Global Code Motion Global Value Numbering” In ACM SIGPLAN Notices, Volume 30, Issue 6, pp 246–257, June 1995
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3. M. Pall. “LuaJIT 2.0 intellectual property disclosure and research opportunities” November 2009 http://lua-users.org/lists/lua-l/2009-11/msg00089.html
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4. M. N. Wegman and F. K. Zadeck. "Constant propagation with conditional branches" ACM Transactions on Programming Languages and Systems, 13(2):181-210, April 1991
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5. C. Wimmer. “Optimized Interval Splitting in a Linear Scan Register Allocator” In VEE '05: Proceedings of the 1st ACM/USENIX international conference on Virtual execution environments, pages 132–141, June 2005
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6. C. Wimmer and M. Franz. “Linear Scan Register Allocation on SSA Form” In CGO '10: Proceedings of the 8-th annual IEEE/ACM international symposium on Code generation and optimization, pages 170–179, April 2010
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