ir/tests/x86_64/mul_005.irt
Dmitry Stogov 7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
2023-06-29 12:42:44 +03:00

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--TEST--
005: mul function
--TARGET--
x86_64
--ARGS--
-S
--CODE--
{
uint32_t c = 2;
l_1 = START(l_4);
uint16_t x = PARAM(l_1, "x", 1);
uint16_t ret = MUL(c, x);
l_4 = RETURN(l_1, ret);
}
--EXPECT--
test:
movw %di, %ax
addw %ax, %ax
retq