Dmitry Stogov c9fa8dfebd Fixed SSA deconstruction ...

Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.

2023-05-17 22:37:45 +03:00

..

args_001.irt

Add support for Windows-64 ABI ("home space")

2023-03-02 13:27:01 +03:00

args_002.irt

Fix register clobbering during argument passing

2022-12-26 18:27:53 +03:00

call2.irt

Improve load fusion, register allocateion and code selection for ADD

2023-02-21 22:55:47 +03:00

call3.irt

Improve load fusion, register allocateion and code selection for ADD

2023-02-21 22:55:47 +03:00

call_002.irt

Extend disassembler to support .rodata section and IP relative data labels

2022-05-26 01:17:02 +03:00

call_003.irt

Improve parallel copy algorithm to support move of single source into multiple destinations

2023-04-26 10:56:55 +03:00

call_alloca.irt

Fuse address calculation into LOAD/STORE

2022-08-24 16:11:04 +03:00

call_vaddr.irt

Fuse address calculation into LOAD/STORE

2022-08-24 16:11:04 +03:00

call-O0.irt

Extend disassembler to support .rodata section and IP relative data labels

2022-05-26 01:17:02 +03:00

call.irt

Extend disassembler to support .rodata section and IP relative data labels

2022-05-26 01:17:02 +03:00

combo_001.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

combo_002.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

combo_003.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

combo_004.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

dce_001.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

dessa_001.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

dessa_002.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

dessa_003.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

fig-O0.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

fig.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

ijmp_001.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

lea_001.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

loop_001.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

loop_002.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

memop_001.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

memop_002.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

memop_003.irt

Validate operand types

2022-06-03 11:23:05 +03:00

memop_004.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

memop_005.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

memop_006.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

memop_007.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

memop_008.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

params_001.irt

Improve load fusion, register allocateion and code selection for ADD

2023-02-21 22:55:47 +03:00

params_002.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

params_003.irt

Avoid reservaton of temporary resiser for argument passing

2023-04-26 12:16:05 +03:00

ra_001.irt

Improve load fusion, register allocateion and code selection for ADD

2023-02-21 22:55:47 +03:00

regset-fib2.irt

Fixed SSA deconstruction

2023-05-17 22:37:45 +03:00

regset-fib.irt

Fixed SSA deconstruction

2023-05-17 22:37:45 +03:00

regset-fibi.irt

Fixed SSA deconstruction

2023-05-17 22:37:45 +03:00

regset-test.irt

Fixed SSA deconstruction

2023-05-17 22:37:45 +03:00

sccp_001.irt

Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32")

2023-02-17 18:11:13 +03:00

sccp_002.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

swap_001.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

swap_002.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

switch_001.irt

Fix buffer overflow

2022-05-26 17:19:43 +03:00

switch_002.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

switch_003.irt

Allow multi-target test suite

2022-05-25 17:38:22 +03:00

tailcall_001.irt

Remove data dependency between TAILCALL and UNREACHABLE

2023-04-13 02:41:28 +03:00

tailcall_002.irt

Remove data dependency between TAILCALL and UNREACHABLE

2023-04-13 02:41:28 +03:00

test64.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

test_mem.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

test_var-O0.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

test_var.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

test-mavx.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

test-O0.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00

test.irt

Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.

2023-03-23 00:47:27 +03:00