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ir/tests/debug
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Dmitry Stogov 7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
2023-06-29 12:42:44 +03:00
..
args_001.irt
Add support for Windows-64 ABI ("home space")
2023-03-02 13:27:01 +03:00
args_002.irt
Fix register clobbering during argument passing
2022-12-26 18:27:53 +03:00
call2.irt
Improve load fusion, register allocateion and code selection for ADD
2023-02-21 22:55:47 +03:00
call3.irt
Improve load fusion, register allocateion and code selection for ADD
2023-02-21 22:55:47 +03:00
call_002.irt
Extend disassembler to support .rodata section and IP relative data labels
2022-05-26 01:17:02 +03:00
call_003.irt
Improve parallel copy algorithm to support move of single source into multiple destinations
2023-04-26 10:56:55 +03:00
call_alloca.irt
Fuse address calculation into LOAD/STORE
2022-08-24 16:11:04 +03:00
call_vaddr.irt
Fuse address calculation into LOAD/STORE
2022-08-24 16:11:04 +03:00
call-O0.irt
Extend disassembler to support .rodata section and IP relative data labels
2022-05-26 01:17:02 +03:00
call.irt
Extend disassembler to support .rodata section and IP relative data labels
2022-05-26 01:17:02 +03:00
combo_001.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
combo_002.irt
Added type compatibility assertion and fixed mistakes in tests
2023-05-22 20:48:07 +03:00
combo_003.irt
Added type compatibility assertion and fixed mistakes in tests
2023-05-22 20:48:07 +03:00
combo_004.irt
Fixed mistakes in GCM algorithm
2023-05-29 17:02:50 +03:00
dce_001.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
dessa_001.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
dessa_002.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
dessa_003.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
fig-O0.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
fig.irt
Fixed incorrect oredering of moves during de-SSA
2023-06-22 12:07:19 +03:00
ijmp_001.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
lea_001.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
loop_001.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
loop_002.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
memop_001.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
memop_002.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
memop_003.irt
Validate operand types
2022-06-03 11:23:05 +03:00
memop_004.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
memop_005.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
memop_006.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
memop_007.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
memop_008.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
memop_009.irt
Fix impossible load fusion
2023-06-20 12:14:52 +03:00
memop_010.irt
Fix impossible load fusion
2023-06-20 12:14:52 +03:00
params_001.irt
Avoid loading of stack parameter to register if this is not necessary
2023-06-09 00:35:15 +03:00
params_002.irt
Better usage of the register hints
2023-06-09 16:26:15 +03:00
params_003.irt
Avoid reservaton of temporary resiser for argument passing
2023-04-26 12:16:05 +03:00
ra_001.irt
Improve load fusion, register allocateion and code selection for ADD
2023-02-21 22:55:47 +03:00
ra_002.irt
Split assign_regs() loop into two versions (with and without spilling).
2023-06-20 08:34:54 +03:00
ra_003.irt
Split assign_regs() loop into two versions (with and without spilling).
2023-06-20 08:34:54 +03:00
regset-fib2.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
regset-fib.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
regset-fibi.irt
Fixed SSA deconstruction
2023-05-17 22:37:45 +03:00
regset-test.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
sccp_001.irt
Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32")
2023-02-17 18:11:13 +03:00
sccp_002.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
swap_001.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
swap_002.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
switch_001.irt
Fix buffer overflow
2022-05-26 17:19:43 +03:00
switch_002.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
switch_003.irt
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
tailcall_001.irt
Remove data dependency between TAILCALL and UNREACHABLE
2023-04-13 02:41:28 +03:00
tailcall_002.irt
Remove data dependency between TAILCALL and UNREACHABLE
2023-04-13 02:41:28 +03:00
test64.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00
test_mem.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test_var-O0.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test_var.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test-mavx.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test-O0.irt
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
2023-03-23 00:47:27 +03:00
test.irt
More accurate spill loads optimization for instructions that reuse op1 register for result
2023-06-29 12:42:44 +03:00