2022-11-08 09:32:46 +01:00
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/*
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* IR - Lightweight JIT Compilation Framework
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* (Public API)
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* Copyright (C) 2022 Zend by Perforce.
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* Authors: Dmitry Stogov <dmitry@php.net>
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*/
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2022-04-05 23:19:23 +02:00
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#ifndef IR_H
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#define IR_H
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2023-03-27 00:29:58 +02:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2022-04-05 23:19:23 +02:00
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#include <inttypes.h>
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#include <stdint.h>
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2022-06-09 23:16:29 +02:00
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#include <stdbool.h>
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2022-04-05 23:19:23 +02:00
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#include <stdio.h>
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2022-09-06 23:04:02 +02:00
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#include <stdlib.h>
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2022-04-05 23:19:23 +02:00
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#define IR_VERSION "0.0.1"
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2023-02-21 00:19:03 +01:00
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#ifdef _WIN32
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/* TODO Handle ARM, too. */
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# if defined(_M_X64)
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# define __SIZEOF_SIZE_T__ 8
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# elif defined(_M_IX86)
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# define __SIZEOF_SIZE_T__ 4
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# endif
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/* Only supported is little endian for any arch on Windows,
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so just fake the same for all. */
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# define __ORDER_LITTLE_ENDIAN__ 1
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# define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
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2023-03-03 12:15:42 +01:00
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# ifndef __has_builtin
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# define __has_builtin(arg) (0)
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# endif
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2023-02-21 00:19:03 +01:00
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#endif
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2022-05-25 16:38:22 +02:00
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#if defined(IR_TARGET_X86)
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# define IR_TARGET "x86"
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#elif defined(IR_TARGET_X64)
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2023-03-01 22:52:51 +01:00
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# ifdef _WIN64
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# define IR_TARGET "Windows-x86_64" /* 64-bit Windows use different ABI and calling convention */
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# else
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# define IR_TARGET "x86_64"
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# endif
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2022-05-31 10:22:31 +02:00
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#elif defined(IR_TARGET_AARCH64)
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# define IR_TARGET "aarch64"
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2022-05-25 16:38:22 +02:00
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#else
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# error "Unknown IR target"
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#endif
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2022-05-27 12:18:04 +02:00
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#if defined(__SIZEOF_SIZE_T__)
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# if __SIZEOF_SIZE_T__ == 8
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# define IR_64 1
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# elif __SIZEOF_SIZE_T__ != 4
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# error "Unknown addr size"
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2022-05-13 08:22:31 +02:00
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# endif
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2022-04-05 23:19:23 +02:00
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#else
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2022-05-27 12:18:04 +02:00
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# error "Unknown addr size"
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2022-04-05 23:19:23 +02:00
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#endif
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#if defined(__BYTE_ORDER__)
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# if defined(__ORDER_LITTLE_ENDIAN__)
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# if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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# define IR_STRUCT_LOHI(lo, hi) struct {lo; hi;}
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# endif
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# endif
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# if defined(__ORDER_BIG_ENDIAN__)
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# if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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# define IR_STRUCT_LOHI(lo, hi) struct {hi; lo;}
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# endif
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# endif
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#endif
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#ifndef IR_STRUCT_LOHI
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# error "Unknown byte order"
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#endif
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2023-02-07 21:14:10 +01:00
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#ifdef __has_attribute
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# if __has_attribute(always_inline)
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# define IR_ALWAYS_INLINE static inline __attribute__((always_inline))
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# endif
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# if __has_attribute(noinline)
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# define IR_NEVER_INLINE __attribute__((noinline))
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# endif
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#else
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# define __has_attribute(x) 0
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#endif
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#ifndef IR_ALWAYS_INLINE
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# define IR_ALWAYS_INLINE static inline
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#endif
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#ifndef IR_NEVER_INLINE
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# define IR_NEVER_INLINE
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#endif
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2022-06-09 23:16:29 +02:00
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#ifdef IR_PHP
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# include "ir_php.h"
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#endif
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2022-04-05 23:19:23 +02:00
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2022-05-27 12:18:04 +02:00
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/* IR Type flags (low 4 bits are used for type size) */
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2022-04-05 23:19:23 +02:00
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#define IR_TYPE_SIGNED (1<<4)
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#define IR_TYPE_UNSIGNED (1<<5)
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#define IR_TYPE_FP (1<<6)
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#define IR_TYPE_SPECIAL (1<<7)
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#define IR_TYPE_BOOL (IR_TYPE_SPECIAL|IR_TYPE_UNSIGNED)
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#define IR_TYPE_ADDR (IR_TYPE_SPECIAL|IR_TYPE_UNSIGNED)
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#define IR_TYPE_CHAR (IR_TYPE_SPECIAL|IR_TYPE_SIGNED)
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2022-05-27 12:18:04 +02:00
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/* List of IR types */
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2022-04-05 23:19:23 +02:00
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#define IR_TYPES(_) \
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2022-04-20 11:00:36 +02:00
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_(BOOL, bool, b, IR_TYPE_BOOL) \
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_(U8, uint8_t, u8, IR_TYPE_UNSIGNED) \
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_(U16, uint16_t, u16, IR_TYPE_UNSIGNED) \
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_(U32, uint32_t, u32, IR_TYPE_UNSIGNED) \
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_(U64, uint64_t, u64, IR_TYPE_UNSIGNED) \
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_(ADDR, uintptr_t, addr, IR_TYPE_ADDR) \
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_(CHAR, char, c, IR_TYPE_CHAR) \
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_(I8, int8_t, i8, IR_TYPE_SIGNED) \
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_(I16, int16_t, i16, IR_TYPE_SIGNED) \
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_(I32, int32_t, i32, IR_TYPE_SIGNED) \
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_(I64, int64_t, i64, IR_TYPE_SIGNED) \
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_(DOUBLE, double, d, IR_TYPE_FP) \
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_(FLOAT, float, f, IR_TYPE_FP) \
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2022-04-05 23:19:23 +02:00
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#define IR_IS_TYPE_UNSIGNED(t) ((t) < IR_CHAR)
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#define IR_IS_TYPE_SIGNED(t) ((t) >= IR_CHAR && (t) < IR_DOUBLE)
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#define IR_IS_TYPE_INT(t) ((t) < IR_DOUBLE)
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#define IR_IS_TYPE_FP(t) ((t) >= IR_DOUBLE)
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2022-05-27 12:18:04 +02:00
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#define IR_TYPE_ENUM(name, type, field, flags) IR_ ## name,
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typedef enum _ir_type {
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IR_VOID,
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IR_TYPES(IR_TYPE_ENUM)
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IR_LAST_TYPE
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} ir_type;
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2022-04-05 23:19:23 +02:00
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/* List of IR opcodes
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* ==================
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*
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* Each instruction is described by a type (opcode, flags, op1_type, op2_type, op3_type)
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*
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* flags
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* -----
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* v - void
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* d - data IR_OP_FLAG_DATA
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* r - ref IR_OP_FLAG_DATA alias
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* c - control IR_OP_FLAG_CONTROL
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2022-06-15 21:48:19 +02:00
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* S - control IR_OP_FLAG_CONTROL + IR_OP_FLAG_BB_START
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2022-06-09 23:16:29 +02:00
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* E - control IR_OP_FLAG_CONTROL + IR_OP_FLAG_BB_END
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2022-06-15 21:48:19 +02:00
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* T - control IR_OP_FLAG_CONTROL + IR_OP_FLAG_BB_END + IR_OP_FLAG_TERMINATOR
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2022-04-05 23:19:23 +02:00
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* l - load IR_OP_FLAG_MEM + IR_OP_FLAG_MEM_LOAD
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* s - store IR_OP_FLAG_MEM + IR_OP_FLAG_STORE
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* x - call IR_OP_FLAG_MEM + IR_OP_FLAG_CALL
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* a - alloc IR_OP_FLAG_MEM + IR_OP_FLAG_ALLOC
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* 0-3 - number of input edges
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2023-04-21 11:40:17 +02:00
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* N - number of arguments is defined in the insn->inputs_count (MERGE, PHI, CALL)
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2022-04-05 23:19:23 +02:00
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* X1-X3 - number of extra data ops
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2022-04-21 10:30:05 +02:00
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* C - commutative operation ("d2C" => IR_OP_FLAG_DATA + IR_OP_FLAG_COMMUTATIVE)
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2022-04-05 23:19:23 +02:00
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*
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* operand types
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* -------------
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* ___ - unused
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* def - reference to a definition op (data-flow use-def dependency edge)
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* ref - memory reference (data-flow use-def dependency edge)
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2022-04-19 21:35:29 +02:00
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* var - variable reference (data-flow use-def dependency edge)
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2022-04-05 23:19:23 +02:00
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* arg - argument referene CALL/TAILCALL/CARG->CARG
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2022-06-16 11:31:23 +02:00
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* src - reference to a previous control region (IF, IF_TRUE, IF_FALSE, MERGE, LOOP_BEGIN, LOOP_END, RETURN)
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2022-04-05 23:19:23 +02:00
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* reg - data-control dependency on region (PHI, VAR, PARAM)
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* ret - reference to a previous RETURN instruction (RETURN)
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* str - string: variable/argument name (VAR, PARAM, CALL, TAILCALL)
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* num - number: argument number (PARAM)
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2022-05-24 11:47:39 +02:00
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* prb - branch probability 1-99 (0 - unspecified): (IF_TRUE, IF_FALSE, CASE_VAL, CASE_DEFAULT)
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2023-01-30 14:33:57 +01:00
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* opt - optional number
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2022-04-05 23:19:23 +02:00
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*
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* The order of IR opcodes is carefully selected for efficient folding.
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* - foldable instruction go first
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* - NOP is never used (code 0 is used as ANY pattern)
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* - CONST is the most often used instruction (encode with 1 bit)
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* - equality inversion: EQ <-> NE => op =^ 1
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* - comparison inversio: [U]LT <-> [U]GT, [U]LE <-> [U]GE => op =^ 3
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*/
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#define IR_OPS(_) \
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/* special op (must be the first !!!) */ \
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_(NOP, v, ___, ___, ___) /* empty instruction */ \
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\
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/* constants reference */ \
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_(C_BOOL, r0, ___, ___, ___) /* constant */ \
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_(C_U8, r0, ___, ___, ___) /* constant */ \
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_(C_U16, r0, ___, ___, ___) /* constant */ \
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_(C_U32, r0, ___, ___, ___) /* constant */ \
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_(C_U64, r0, ___, ___, ___) /* constant */ \
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_(C_ADDR, r0, ___, ___, ___) /* constant */ \
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_(C_CHAR, r0, ___, ___, ___) /* constant */ \
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_(C_I8, r0, ___, ___, ___) /* constant */ \
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_(C_I16, r0, ___, ___, ___) /* constant */ \
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_(C_I32, r0, ___, ___, ___) /* constant */ \
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_(C_I64, r0, ___, ___, ___) /* constant */ \
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_(C_DOUBLE, r0, ___, ___, ___) /* constant */ \
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_(C_FLOAT, r0, ___, ___, ___) /* constant */ \
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\
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/* equality ops */ \
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2022-04-21 10:30:05 +02:00
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_(EQ, d2C, def, def, ___) /* equal */ \
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_(NE, d2C, def, def, ___) /* not equal */ \
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2022-04-05 23:19:23 +02:00
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\
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/* comparison ops (order matters, LT must be a modulo of 4 !!!) */ \
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_(LT, d2, def, def, ___) /* less */ \
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_(GE, d2, def, def, ___) /* greater or equal */ \
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_(LE, d2, def, def, ___) /* less or equal */ \
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_(GT, d2, def, def, ___) /* greater */ \
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_(ULT, d2, def, def, ___) /* unsigned less */ \
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_(UGE, d2, def, def, ___) /* unsigned greater or equal */ \
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_(ULE, d2, def, def, ___) /* unsigned less or equal */ \
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_(UGT, d2, def, def, ___) /* unsigned greater */ \
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\
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/* arithmetic ops */ \
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2022-04-21 10:30:05 +02:00
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_(ADD, d2C, def, def, ___) /* addition */ \
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2022-04-05 23:19:23 +02:00
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_(SUB, d2, def, def, ___) /* subtraction (must be ADD+1) */ \
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2022-04-21 10:30:05 +02:00
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_(MUL, d2C, def, def, ___) /* multiplication */ \
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2022-04-05 23:19:23 +02:00
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_(DIV, d2, def, def, ___) /* division */ \
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_(MOD, d2, def, def, ___) /* modulo */ \
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_(NEG, d1, def, ___, ___) /* change sign */ \
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_(ABS, d1, def, ___, ___) /* absolute value */ \
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/* (LDEXP, MIN, MAX, FPMATH) */ \
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\
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2022-05-20 08:00:13 +02:00
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/* type conversion ops */ \
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2022-05-20 00:01:48 +02:00
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_(SEXT, d1, def, ___, ___) /* sign extension */ \
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_(ZEXT, d1, def, ___, ___) /* zero extension */ \
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2022-05-20 08:00:13 +02:00
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_(TRUNC, d1, def, ___, ___) /* truncates to int type */ \
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_(BITCAST, d1, def, ___, ___) /* binary representation */ \
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2022-05-20 00:01:48 +02:00
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_(INT2FP, d1, def, ___, ___) /* int to float conversion */ \
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_(FP2INT, d1, def, ___, ___) /* float to int conversion */ \
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2022-05-20 08:00:13 +02:00
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_(FP2FP, d1, def, ___, ___) /* float to float conversion */ \
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2022-04-05 23:19:23 +02:00
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\
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2022-05-27 12:18:04 +02:00
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/* overflow-check */ \
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2022-04-21 10:30:05 +02:00
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_(ADD_OV, d2C, def, def, ___) /* addition */ \
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2022-04-05 23:19:23 +02:00
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_(SUB_OV, d2, def, def, ___) /* subtraction */ \
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2022-04-21 10:30:05 +02:00
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_(MUL_OV, d2C, def, def, ___) /* multiplication */ \
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2022-04-05 23:19:23 +02:00
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_(OVERFLOW, d1, def, ___, ___) /* overflow check add/sub/mul */ \
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\
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/* bitwise and shift ops */ \
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_(NOT, d1, def, ___, ___) /* bitwise NOT */ \
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2022-04-21 10:30:05 +02:00
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_(OR, d2C, def, def, ___) /* bitwise OR */ \
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_(AND, d2C, def, def, ___) /* bitwise AND */ \
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_(XOR, d2C, def, def, ___) /* bitwise XOR */ \
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2022-04-05 23:19:23 +02:00
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_(SHL, d2, def, def, ___) /* logic shift left */ \
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_(SHR, d2, def, def, ___) /* logic shift right */ \
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_(SAR, d2, def, def, ___) /* arithmetic shift right */ \
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_(ROL, d2, def, def, ___) /* rotate left */ \
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_(ROR, d2, def, def, ___) /* rotate right */ \
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_(BSWAP, d1, def, ___, ___) /* byte swap */ \
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\
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/* branch-less conditional ops */ \
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2022-04-21 10:30:05 +02:00
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_(MIN, d2C, def, def, ___) /* min(op1, op2) */ \
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_(MAX, d2C, def, def, ___) /* max(op1, op2) */ \
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2022-04-05 23:19:23 +02:00
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_(COND, d3, def, def, def) /* op1 ? op2 : op3 */ \
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\
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/* data-flow and miscellaneous ops */ \
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2023-04-21 11:40:17 +02:00
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_(PHI, dN, reg, def, def) /* SSA Phi function */ \
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2022-10-21 16:16:25 +02:00
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_(COPY, d1X1, def, opt, ___) /* COPY (last foldable op) */ \
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2022-04-05 23:19:23 +02:00
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_(PI, d2, reg, def, ___) /* e-SSA Pi constraint ??? */ \
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/* (USE, RENAME) */ \
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\
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/* data ops */ \
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_(PARAM, r1X2, reg, str, num) /* incoming parameter proj. */ \
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_(VAR, r1X1, reg, str, ___) /* local variable */ \
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2022-06-23 12:14:30 +02:00
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_(FUNC_ADDR, r0, ___, ___, ___) /* constant func ref */ \
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2022-04-05 23:19:23 +02:00
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_(FUNC, r0, ___, ___, ___) /* constant func ref */ \
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_(STR, r0, ___, ___, ___) /* constant str ref */ \
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\
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/* call ops */ \
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_(CALL, xN, src, def, def) /* CALL(src, func, args...) */ \
|
|
|
|
_(TAILCALL, xN, src, def, def) /* CALL+RETURN */ \
|
|
|
|
\
|
|
|
|
/* memory reference and load/store ops */ \
|
2022-04-19 22:42:05 +02:00
|
|
|
_(ALLOCA, a2, src, def, ___) /* alloca(def) */ \
|
2022-12-07 11:09:00 +01:00
|
|
|
_(AFREE, a2, src, def, ___) /* revert alloca(def) */ \
|
2022-04-20 11:00:36 +02:00
|
|
|
_(VADDR, d1, var, ___, ___) /* load address of local var */ \
|
2022-04-19 21:35:29 +02:00
|
|
|
_(VLOAD, l2, src, var, ___) /* load value of local var */ \
|
|
|
|
_(VSTORE, s3, src, var, def) /* store value to local var */ \
|
2023-01-30 14:33:57 +01:00
|
|
|
_(RLOAD, l1X2, src, num, opt) /* load value from register */ \
|
2022-11-08 13:25:01 +01:00
|
|
|
_(RSTORE, s2X1, src, def, num) /* store value into register */ \
|
2022-04-11 21:39:52 +02:00
|
|
|
_(LOAD, l2, src, ref, ___) /* load from memory */ \
|
|
|
|
_(STORE, s3, src, ref, def) /* store to memory */ \
|
2022-06-27 23:03:06 +02:00
|
|
|
_(TLS, l1X2, src, num, num) /* thread local variable */ \
|
2022-07-20 16:59:44 +02:00
|
|
|
_(TRAP, x1, src, ___, ___) /* DebugBreak */ \
|
2022-04-05 23:19:23 +02:00
|
|
|
/* memory reference ops (A, H, U, S, TMP, STR, NEW, X, V) ??? */ \
|
|
|
|
\
|
2023-03-15 21:49:50 +01:00
|
|
|
/* guards */ \
|
|
|
|
_(GUARD, c3, src, def, def) /* IF without second successor */ \
|
|
|
|
_(GUARD_NOT , c3, src, def, def) /* IF without second successor */ \
|
|
|
|
\
|
|
|
|
/* deoptimization */ \
|
|
|
|
_(SNAPSHOT, xN, src, def, def) /* SNAPSHOT(src, args...) */ \
|
|
|
|
\
|
2022-04-05 23:19:23 +02:00
|
|
|
/* control-flow nodes */ \
|
2023-03-17 07:02:37 +01:00
|
|
|
_(START, S0X1, ret, ___, ___) /* function start */ \
|
|
|
|
_(ENTRY, S1X1, src, num, ___) /* entry with a fake src edge */ \
|
2022-06-15 21:48:19 +02:00
|
|
|
_(BEGIN, S1, src, ___, ___) /* block start */ \
|
|
|
|
_(IF_TRUE, S1X1, src, prb, ___) /* IF TRUE proj. */ \
|
|
|
|
_(IF_FALSE, S1X1, src, prb, ___) /* IF FALSE proj. */ \
|
|
|
|
_(CASE_VAL, S2X1, src, def, prb) /* switch proj. */ \
|
|
|
|
_(CASE_DEFAULT, S1X1, src, prb, ___) /* switch proj. */ \
|
|
|
|
_(MERGE, SN, src, src, src) /* control merge */ \
|
2022-06-16 11:31:23 +02:00
|
|
|
_(LOOP_BEGIN, SN, src, src, src) /* loop start */ \
|
2022-11-09 19:52:08 +01:00
|
|
|
_(END, E1, src, ___, ___) /* block end */ \
|
2023-03-22 22:47:27 +01:00
|
|
|
_(LOOP_END, E1, src, ___, ___) /* loop end */ \
|
2022-11-09 19:52:08 +01:00
|
|
|
_(IF, E2, src, def, ___) /* conditional control split */ \
|
|
|
|
_(SWITCH, E2, src, def, ___) /* multi-way control split */ \
|
|
|
|
_(RETURN, T2X1, src, def, ret) /* function return */ \
|
2022-06-15 21:48:19 +02:00
|
|
|
_(IJMP, T2X1, src, def, ret) /* computed goto */ \
|
2023-04-13 01:41:28 +02:00
|
|
|
_(UNREACHABLE, T1X2, src, ___, ret) /* unreachable (tailcall, etc) */ \
|
2022-04-05 23:19:23 +02:00
|
|
|
\
|
2022-10-26 15:06:16 +02:00
|
|
|
/* deoptimization helper */ \
|
|
|
|
_(EXITCALL, x2, src, def, ___) /* save CPU regs and call op2 */ \
|
2022-09-23 11:22:59 +02:00
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
#define IR_OP_ENUM(name, flags, op1, op2, op3) IR_ ## name,
|
|
|
|
|
|
|
|
typedef enum _ir_op {
|
|
|
|
IR_OPS(IR_OP_ENUM)
|
2022-06-09 23:16:29 +02:00
|
|
|
#ifdef IR_PHP
|
|
|
|
IR_PHP_OPS(IR_OP_ENUM)
|
|
|
|
#endif
|
2022-04-05 23:19:23 +02:00
|
|
|
IR_LAST_OP
|
|
|
|
} ir_op;
|
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
/* IR Opcode and Type Union */
|
|
|
|
#define IR_OPT_OP_MASK 0x00ff
|
|
|
|
#define IR_OPT_TYPE_MASK 0xff00
|
|
|
|
#define IR_OPT_TYPE_SHIFT 8
|
2023-04-21 11:40:17 +02:00
|
|
|
#define IR_OPT_INPUTS_SHIFT 16
|
2022-05-27 12:18:04 +02:00
|
|
|
|
|
|
|
#define IR_OPT(op, type) ((uint16_t)(op) | ((uint16_t)(type) << IR_OPT_TYPE_SHIFT))
|
2023-04-21 11:40:17 +02:00
|
|
|
#define IR_OPTX(op, type, n) ((uint32_t)(op) | ((uint32_t)(type) << IR_OPT_TYPE_SHIFT) | ((uint32_t)(n) << IR_OPT_INPUTS_SHIFT))
|
2022-05-27 12:18:04 +02:00
|
|
|
#define IR_OPT_TYPE(opt) (((opt) & IR_OPT_TYPE_MASK) >> IR_OPT_TYPE_SHIFT)
|
|
|
|
|
|
|
|
/* IR References */
|
2022-04-05 23:19:23 +02:00
|
|
|
typedef int32_t ir_ref;
|
|
|
|
|
|
|
|
#define IR_IS_CONST_REF(ref) ((ref) < 0)
|
|
|
|
|
|
|
|
#define IR_UNUSED 0
|
|
|
|
#define IR_NULL (-1)
|
|
|
|
#define IR_FALSE (-2)
|
|
|
|
#define IR_TRUE (-3)
|
2022-05-27 12:18:04 +02:00
|
|
|
#define IR_LAST_FOLDABLE_OP IR_COPY
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2023-03-27 00:54:08 +02:00
|
|
|
#define IR_CONSTS_LIMIT_MIN (-(IR_TRUE - 1))
|
|
|
|
#define IR_INSNS_LIMIT_MIN (IR_UNUSED + 1)
|
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
/* IR Constant Value */
|
2023-02-21 00:19:03 +01:00
|
|
|
#ifndef IR_64
|
|
|
|
# define ADDR_MEMBER uintptr_t addr;
|
|
|
|
#else
|
|
|
|
# define ADDR_MEMBER
|
|
|
|
#endif
|
2022-04-05 23:19:23 +02:00
|
|
|
typedef union _ir_val {
|
|
|
|
double d;
|
|
|
|
uint64_t u64;
|
|
|
|
int64_t i64;
|
|
|
|
#ifdef IR_64
|
|
|
|
uintptr_t addr;
|
|
|
|
#endif
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
uint32_t u32;
|
|
|
|
int32_t i32;
|
|
|
|
float f;
|
2023-02-21 00:19:03 +01:00
|
|
|
ADDR_MEMBER
|
2022-04-05 23:19:23 +02:00
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
uint16_t u16;
|
|
|
|
int16_t i16;
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
uint8_t u8;
|
|
|
|
int8_t i8;
|
|
|
|
bool b;
|
|
|
|
char c;
|
|
|
|
},
|
|
|
|
uint8_t u8_hi
|
|
|
|
);
|
|
|
|
},
|
|
|
|
uint16_t u16_hi
|
|
|
|
);
|
|
|
|
},
|
|
|
|
uint32_t u32_hi
|
|
|
|
);
|
|
|
|
} ir_val;
|
2023-02-21 00:19:03 +01:00
|
|
|
#undef ADDR_MEMBER
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-06-23 10:25:47 +02:00
|
|
|
/* IR constant flags */
|
|
|
|
#define IR_CONST_EMIT (1<<0)
|
2022-06-23 12:14:30 +02:00
|
|
|
#define IR_CONST_FASTCALL_FUNC (1<<1)
|
2023-03-02 15:56:15 +01:00
|
|
|
#define IR_CONST_VARARG_FUNC (1<<2)
|
2022-06-23 10:25:47 +02:00
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
/* IR Instruction */
|
2022-04-05 23:19:23 +02:00
|
|
|
typedef struct _ir_insn {
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
uint8_t op,
|
2023-02-21 00:19:03 +01:00
|
|
|
uint8_t type
|
2022-04-05 23:19:23 +02:00
|
|
|
);
|
|
|
|
uint16_t opt;
|
|
|
|
},
|
|
|
|
union {
|
2023-04-21 11:40:17 +02:00
|
|
|
uint16_t inputs_count; /* number of input control edges for MERGE, PHI, CALL, TAILCALL */
|
2022-04-05 23:19:23 +02:00
|
|
|
uint16_t prev_insn_offset; /* 16-bit backward offset from current instruction for CSE */
|
2022-06-23 10:25:47 +02:00
|
|
|
uint16_t const_flags; /* flag to emit constant in rodat section */
|
2022-04-05 23:19:23 +02:00
|
|
|
}
|
|
|
|
);
|
|
|
|
uint32_t optx;
|
|
|
|
ir_ref ops[1];
|
|
|
|
},
|
|
|
|
union {
|
|
|
|
ir_ref op1;
|
|
|
|
ir_ref prev_const;
|
|
|
|
}
|
|
|
|
);
|
|
|
|
union {
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
ir_ref op2,
|
|
|
|
ir_ref op3
|
|
|
|
);
|
|
|
|
ir_val val;
|
|
|
|
};
|
|
|
|
} ir_insn;
|
|
|
|
|
2022-09-06 23:04:02 +02:00
|
|
|
/* IR Hash Tables API (private) */
|
|
|
|
typedef struct _ir_hashtab ir_hashtab;
|
|
|
|
|
|
|
|
/* IR String Tables API (implementation in ir_strtab.c) */
|
2022-04-05 23:19:23 +02:00
|
|
|
typedef struct _ir_strtab {
|
|
|
|
void *data;
|
|
|
|
uint32_t mask;
|
|
|
|
uint32_t size;
|
|
|
|
uint32_t count;
|
|
|
|
uint32_t pos;
|
|
|
|
char *buf;
|
|
|
|
uint32_t buf_size;
|
|
|
|
uint32_t buf_top;
|
|
|
|
} ir_strtab;
|
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
#define ir_strtab_count(strtab) (strtab)->count
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
typedef void (*ir_strtab_apply_t)(const char *str, uint32_t len, ir_ref val);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
void ir_strtab_init(ir_strtab *strtab, uint32_t count, uint32_t buf_size);
|
|
|
|
ir_ref ir_strtab_lookup(ir_strtab *strtab, const char *str, uint32_t len, ir_ref val);
|
2023-03-28 12:18:12 +02:00
|
|
|
ir_ref ir_strtab_find(const ir_strtab *strtab, const char *str, uint32_t len);
|
2022-05-27 12:18:04 +02:00
|
|
|
ir_ref ir_strtab_update(ir_strtab *strtab, const char *str, uint32_t len, ir_ref val);
|
2023-03-28 12:18:12 +02:00
|
|
|
const char *ir_strtab_str(const ir_strtab *strtab, ir_ref idx);
|
|
|
|
void ir_strtab_apply(const ir_strtab *strtab, ir_strtab_apply_t func);
|
2022-05-27 12:18:04 +02:00
|
|
|
void ir_strtab_free(ir_strtab *strtab);
|
|
|
|
|
|
|
|
/* IR Context Flags */
|
2023-03-27 00:51:05 +02:00
|
|
|
#define IR_FUNCTION (1<<0) /* Generate a function. */
|
|
|
|
#define IR_FASTCALL_FUNC (1<<1) /* Generate a function with fastcall calling convention, x86 32-bit only. */
|
|
|
|
#define IR_SKIP_PROLOGUE (1<<2) /* Don't generate function prologue. */
|
2023-02-14 12:07:54 +01:00
|
|
|
#define IR_USE_FRAME_POINTER (1<<3)
|
|
|
|
#define IR_PREALLOCATED_STACK (1<<4)
|
|
|
|
#define IR_HAS_ALLOCA (1<<5)
|
|
|
|
#define IR_HAS_CALLS (1<<6)
|
|
|
|
#define IR_NO_STACK_COMBINE (1<<7)
|
|
|
|
#define IR_START_BR_TARGET (1<<8)
|
|
|
|
#define IR_ENTRY_BR_TARGET (1<<9)
|
|
|
|
#define IR_GEN_ENDBR (1<<10)
|
|
|
|
#define IR_MERGE_EMPTY_ENTRIES (1<<11)
|
|
|
|
|
|
|
|
#define IR_IRREDUCIBLE_CFG (1<<15)
|
|
|
|
|
|
|
|
#define IR_OPT_FOLDING (1<<16)
|
|
|
|
#define IR_OPT_CFG (1<<17) /* merge BBs, by remove END->BEGIN nodes during CFG construction */
|
|
|
|
#define IR_OPT_CODEGEN (1<<18)
|
|
|
|
#define IR_OPT_IN_SCCP (1<<19)
|
|
|
|
#define IR_LINEAR (1<<20)
|
|
|
|
#define IR_GEN_NATIVE (1<<21)
|
|
|
|
#define IR_GEN_C (1<<22)
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-11-18 10:47:15 +01:00
|
|
|
/* Temporary: Live Ranges */
|
|
|
|
#define IR_LR_HAVE_VARS (1<<25)
|
|
|
|
#define IR_LR_HAVE_DESSA_MOVES (1<<26)
|
|
|
|
|
|
|
|
/* Temporary: Register Allocator */
|
|
|
|
#define IR_RA_HAVE_SPLITS (1<<25)
|
|
|
|
#define IR_RA_HAVE_SPILLS (1<<26)
|
|
|
|
|
2022-04-27 13:47:52 +02:00
|
|
|
/* debug relted */
|
|
|
|
#ifdef IR_DEBUG
|
2022-05-24 17:04:38 +02:00
|
|
|
# define IR_DEBUG_SCCP (1<<27)
|
|
|
|
# define IR_DEBUG_GCM (1<<28)
|
|
|
|
# define IR_DEBUG_SCHEDULE (1<<29)
|
2022-04-27 13:47:52 +02:00
|
|
|
# define IR_DEBUG_RA (1<<30)
|
|
|
|
#endif
|
|
|
|
|
2023-02-10 11:34:46 +01:00
|
|
|
typedef struct _ir_ctx ir_ctx;
|
2022-05-27 12:18:04 +02:00
|
|
|
typedef struct _ir_use_list ir_use_list;
|
|
|
|
typedef struct _ir_block ir_block;
|
2023-04-13 12:47:16 +02:00
|
|
|
typedef struct _ir_arena ir_arena;
|
2022-04-05 23:19:23 +02:00
|
|
|
typedef struct _ir_live_interval ir_live_interval;
|
2023-04-13 10:42:47 +02:00
|
|
|
typedef struct _ir_live_range ir_live_range;
|
2022-05-05 21:35:39 +02:00
|
|
|
typedef int8_t ir_regs[4];
|
|
|
|
|
2023-02-10 11:34:46 +01:00
|
|
|
typedef void (*ir_snapshot_create_t)(ir_ctx *ctx, ir_ref addr);
|
|
|
|
|
|
|
|
struct _ir_ctx {
|
2023-03-28 12:18:12 +02:00
|
|
|
ir_insn *ir_base; /* two directional array - instructions grow down, constants grow up */
|
|
|
|
ir_ref insns_count; /* number of instructins stored in instructions buffer */
|
|
|
|
ir_ref insns_limit; /* size of allocated instructions buffer (it's extended when overflow) */
|
|
|
|
ir_ref consts_count; /* number of constants stored in constants buffer */
|
|
|
|
ir_ref consts_limit; /* size of allocated constants buffer (it's extended when overflow) */
|
|
|
|
uint32_t flags; /* IR context flags (see IR_* defines above) */
|
2023-04-18 08:54:35 +02:00
|
|
|
uint32_t mflags; /* CPU specific flags (see IR_X86_... macros below) */
|
2023-03-28 12:18:12 +02:00
|
|
|
ir_ref fold_cse_limit; /* CSE finds identical insns backward from "insn_count" to "fold_cse_limit" */
|
|
|
|
ir_insn fold_insn; /* temporary storage for folding engine */
|
2022-09-15 14:26:43 +02:00
|
|
|
ir_hashtab *binding;
|
2023-03-28 12:18:12 +02:00
|
|
|
ir_use_list *use_lists; /* def->use lists for each instruction */
|
|
|
|
ir_ref *use_edges; /* the actual uses: use = ctx->use_edges[ctx->use_lists[def].refs + n] */
|
|
|
|
ir_ref use_edges_count; /* number of elements in use_edges[] array */
|
|
|
|
uint32_t cfg_blocks_count; /* number of elements in cfg_blocks[] array */
|
|
|
|
uint32_t cfg_edges_count; /* number of elements in cfg_edges[] array */
|
|
|
|
ir_block *cfg_blocks; /* list of basic blocks (starts from 1) */
|
|
|
|
uint32_t *cfg_edges; /* the actual basic blocks predecessors and successors edges */
|
|
|
|
uint32_t *cfg_map; /* map of instructions to basic block number */
|
|
|
|
uint32_t *rules; /* array of target specific code-generation rules (for each instruction) */
|
2022-05-25 11:02:31 +02:00
|
|
|
uint32_t *vregs;
|
2022-11-08 21:09:35 +01:00
|
|
|
ir_ref vregs_count;
|
2023-03-28 12:18:12 +02:00
|
|
|
int32_t spill_base; /* base register for special spill area (e.g. PHP VM frame pointer) */
|
|
|
|
uint64_t fixed_regset; /* fixed registers, excluded for regular register allocation */
|
2023-02-17 13:52:26 +01:00
|
|
|
int32_t fixed_stack_red_zone; /* reusable stack allocated by caller (default 0) */
|
|
|
|
int32_t fixed_stack_frame_size; /* fixed stack allocated by generated code for spills and registers save/restore */
|
|
|
|
int32_t fixed_call_stack_size; /* fixed preallocated stack for parameter passing (default 0) */
|
|
|
|
uint64_t fixed_save_regset; /* registers that always saved/restored in prologue/epilugue */
|
2022-05-25 11:02:31 +02:00
|
|
|
ir_live_interval **live_intervals;
|
2023-04-13 12:47:16 +02:00
|
|
|
ir_arena *arena;
|
2023-04-13 10:42:47 +02:00
|
|
|
ir_live_range *unused_ranges;
|
2022-05-25 11:02:31 +02:00
|
|
|
ir_regs *regs;
|
2022-11-18 11:59:49 +01:00
|
|
|
ir_ref *prev_ref;
|
2023-02-10 11:34:46 +01:00
|
|
|
union {
|
|
|
|
void *data;
|
2023-03-28 12:18:12 +02:00
|
|
|
ir_ref control; /* used by IR construction API (see ir_builder.h) */
|
2023-03-29 00:21:54 +02:00
|
|
|
ir_ref bb_start; /* used by target CPU instruction matcher */
|
2023-02-10 11:34:46 +01:00
|
|
|
};
|
|
|
|
ir_snapshot_create_t snapshot_create;
|
2022-05-26 00:17:02 +02:00
|
|
|
uint32_t rodata_offset;
|
|
|
|
uint32_t jmp_table_offset;
|
2023-03-17 07:02:37 +01:00
|
|
|
uint32_t entries_count;
|
|
|
|
ir_ref *entries;
|
2023-03-21 11:45:37 +01:00
|
|
|
void *osr_entry_loads;
|
2022-06-10 10:30:19 +02:00
|
|
|
void *code_buffer;
|
|
|
|
size_t code_buffer_size;
|
2022-05-25 11:02:31 +02:00
|
|
|
ir_strtab strtab;
|
2022-05-27 12:18:04 +02:00
|
|
|
ir_ref prev_insn_chain[IR_LAST_FOLDABLE_OP + 1];
|
2022-05-25 11:02:31 +02:00
|
|
|
ir_ref prev_const_chain[IR_LAST_TYPE];
|
2023-02-10 11:34:46 +01:00
|
|
|
};
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
/* Basic IR Construction API (implementation in ir.c) */
|
2023-03-27 01:09:35 +02:00
|
|
|
void ir_init(ir_ctx *ctx, uint32_t flags, ir_ref consts_limit, ir_ref insns_limit);
|
2022-05-27 12:18:04 +02:00
|
|
|
void ir_free(ir_ctx *ctx);
|
|
|
|
void ir_truncate(ir_ctx *ctx);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
ir_ref ir_const(ir_ctx *ctx, ir_val val, uint8_t type);
|
|
|
|
ir_ref ir_const_i8(ir_ctx *ctx, int8_t c);
|
|
|
|
ir_ref ir_const_i16(ir_ctx *ctx, int16_t c);
|
|
|
|
ir_ref ir_const_i32(ir_ctx *ctx, int32_t c);
|
|
|
|
ir_ref ir_const_i64(ir_ctx *ctx, int64_t c);
|
|
|
|
ir_ref ir_const_u8(ir_ctx *ctx, uint8_t c);
|
|
|
|
ir_ref ir_const_u16(ir_ctx *ctx, uint16_t c);
|
|
|
|
ir_ref ir_const_u32(ir_ctx *ctx, uint32_t c);
|
|
|
|
ir_ref ir_const_u64(ir_ctx *ctx, uint64_t c);
|
|
|
|
ir_ref ir_const_bool(ir_ctx *ctx, bool c);
|
|
|
|
ir_ref ir_const_char(ir_ctx *ctx, char c);
|
|
|
|
ir_ref ir_const_float(ir_ctx *ctx, float c);
|
|
|
|
ir_ref ir_const_double(ir_ctx *ctx, double c);
|
|
|
|
ir_ref ir_const_addr(ir_ctx *ctx, uintptr_t c);
|
2022-06-23 12:14:30 +02:00
|
|
|
ir_ref ir_const_func_addr(ir_ctx *ctx, uintptr_t c, uint16_t flags);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-06-23 12:14:30 +02:00
|
|
|
ir_ref ir_const_func(ir_ctx *ctx, ir_ref str, uint16_t flags);
|
2022-04-05 23:19:23 +02:00
|
|
|
ir_ref ir_const_str(ir_ctx *ctx, ir_ref str);
|
|
|
|
|
2022-11-09 22:24:33 +01:00
|
|
|
ir_ref ir_unique_const_addr(ir_ctx *ctx, uintptr_t c);
|
|
|
|
|
2023-03-28 12:18:12 +02:00
|
|
|
void ir_print_const(const ir_ctx *ctx, const ir_insn *insn, FILE *f);
|
2022-05-27 12:18:04 +02:00
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
ir_ref ir_str(ir_ctx *ctx, const char *s);
|
|
|
|
ir_ref ir_strl(ir_ctx *ctx, const char *s, size_t len);
|
2023-03-28 12:18:12 +02:00
|
|
|
const char *ir_get_str(const ir_ctx *ctx, ir_ref idx);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
ir_ref ir_emit(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2, ir_ref op3);
|
2022-06-21 10:24:42 +02:00
|
|
|
|
|
|
|
ir_ref ir_emit0(ir_ctx *ctx, uint32_t opt);
|
|
|
|
ir_ref ir_emit1(ir_ctx *ctx, uint32_t opt, ir_ref op1);
|
|
|
|
ir_ref ir_emit2(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2);
|
|
|
|
ir_ref ir_emit3(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2, ir_ref op3);
|
|
|
|
|
2022-11-08 21:09:35 +01:00
|
|
|
ir_ref ir_emit_N(ir_ctx *ctx, uint32_t opt, int32_t count);
|
|
|
|
void ir_set_op(ir_ctx *ctx, ir_ref ref, int32_t n, ir_ref val);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2023-02-07 21:14:10 +01:00
|
|
|
IR_ALWAYS_INLINE void ir_set_op1(ir_ctx *ctx, ir_ref ref, ir_ref val)
|
2022-11-08 16:17:29 +01:00
|
|
|
{
|
|
|
|
ctx->ir_base[ref].op1 = val;
|
|
|
|
}
|
|
|
|
|
2023-02-07 21:14:10 +01:00
|
|
|
IR_ALWAYS_INLINE void ir_set_op2(ir_ctx *ctx, ir_ref ref, ir_ref val)
|
2022-11-08 16:17:29 +01:00
|
|
|
{
|
|
|
|
ctx->ir_base[ref].op2 = val;
|
|
|
|
}
|
|
|
|
|
2023-02-07 21:14:10 +01:00
|
|
|
IR_ALWAYS_INLINE void ir_set_op3(ir_ctx *ctx, ir_ref ref, ir_ref val)
|
2022-11-08 16:17:29 +01:00
|
|
|
{
|
|
|
|
ctx->ir_base[ref].op3 = val;
|
|
|
|
}
|
|
|
|
|
2023-03-28 12:18:12 +02:00
|
|
|
IR_ALWAYS_INLINE ir_ref ir_insn_op(const ir_insn *insn, int32_t n)
|
2022-11-08 16:17:29 +01:00
|
|
|
{
|
2023-03-28 12:18:12 +02:00
|
|
|
const ir_ref *p = insn->ops + n;
|
2022-11-08 16:17:29 +01:00
|
|
|
return *p;
|
|
|
|
}
|
|
|
|
|
2023-02-07 21:14:10 +01:00
|
|
|
IR_ALWAYS_INLINE void ir_insn_set_op(ir_insn *insn, int32_t n, ir_ref val)
|
2022-11-08 16:17:29 +01:00
|
|
|
{
|
|
|
|
ir_ref *p = insn->ops + n;
|
|
|
|
*p = val;
|
|
|
|
}
|
|
|
|
|
2022-06-21 10:24:42 +02:00
|
|
|
ir_ref ir_fold(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2, ir_ref op3);
|
|
|
|
|
|
|
|
ir_ref ir_fold0(ir_ctx *ctx, uint32_t opt);
|
|
|
|
ir_ref ir_fold1(ir_ctx *ctx, uint32_t opt, ir_ref op1);
|
|
|
|
ir_ref ir_fold2(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2);
|
|
|
|
ir_ref ir_fold3(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2, ir_ref op3);
|
|
|
|
|
|
|
|
ir_ref ir_param(ir_ctx *ctx, ir_type type, ir_ref region, const char *name, int pos);
|
|
|
|
ir_ref ir_var(ir_ctx *ctx, ir_type type, ir_ref region, const char *name);
|
2022-10-21 16:16:25 +02:00
|
|
|
ir_ref ir_bind(ir_ctx *ctx, ir_ref var, ir_ref def);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
/* Def -> Use lists */
|
|
|
|
void ir_build_def_use_lists(ir_ctx *ctx);
|
|
|
|
|
|
|
|
/* CFG - Control Flow Graph (implementation in ir_cfg.c) */
|
|
|
|
int ir_build_cfg(ir_ctx *ctx);
|
2022-11-29 18:02:07 +01:00
|
|
|
int ir_remove_unreachable_blocks(ir_ctx *ctx);
|
2022-04-05 23:19:23 +02:00
|
|
|
int ir_build_dominators_tree(ir_ctx *ctx);
|
|
|
|
int ir_find_loops(ir_ctx *ctx);
|
2022-05-23 23:43:35 +02:00
|
|
|
int ir_schedule_blocks(ir_ctx *ctx);
|
2022-11-24 10:55:16 +01:00
|
|
|
void ir_build_prev_refs(ir_ctx *ctx);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
/* SCCP - Sparse Conditional Constant Propagation (implementation in ir_sccp.c) */
|
|
|
|
int ir_sccp(ir_ctx *ctx);
|
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
/* GCM - Global Code Motion and scheduling (implementation in ir_gcm.c) */
|
2022-04-05 23:19:23 +02:00
|
|
|
int ir_gcm(ir_ctx *ctx);
|
|
|
|
int ir_schedule(ir_ctx *ctx);
|
|
|
|
|
|
|
|
/* Liveness & Register Allocation (implementation in ir_ra.c) */
|
2023-01-30 14:33:57 +01:00
|
|
|
#define IR_REG_NONE -1
|
|
|
|
#define IR_REG_SPILL_LOAD (1<<6)
|
|
|
|
#define IR_REG_SPILL_STORE (1<<6)
|
|
|
|
#define IR_REG_NUM(r) \
|
|
|
|
((r) == IR_REG_NONE ? IR_REG_NONE : ((r) & ~(IR_REG_SPILL_LOAD|IR_REG_SPILL_STORE)))
|
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
int ir_assign_virtual_registers(ir_ctx *ctx);
|
|
|
|
int ir_compute_live_ranges(ir_ctx *ctx);
|
|
|
|
int ir_coalesce(ir_ctx *ctx);
|
|
|
|
int ir_compute_dessa_moves(ir_ctx *ctx);
|
2022-05-27 12:18:04 +02:00
|
|
|
int ir_reg_alloc(ir_ctx *ctx);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-10-21 16:16:25 +02:00
|
|
|
int ir_regs_number(void);
|
|
|
|
bool ir_reg_is_int(int32_t reg);
|
|
|
|
const char *ir_reg_name(int8_t reg, ir_type type);
|
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
/* Target CPU instruction selection and code geneartion (see ir_x86.c) */
|
|
|
|
int ir_match(ir_ctx *ctx);
|
2022-05-27 12:18:04 +02:00
|
|
|
void *ir_emit_code(ir_ctx *ctx, size_t *size);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
/* Target CPU disassembler (implementation in ir_disasm.c) */
|
2022-05-27 12:18:04 +02:00
|
|
|
int ir_disasm_init(void);
|
2022-04-05 23:19:23 +02:00
|
|
|
void ir_disasm_free(void);
|
|
|
|
void ir_disasm_add_symbol(const char *name, uint64_t addr, uint64_t size);
|
2022-05-27 12:18:04 +02:00
|
|
|
int ir_disasm(const char *name,
|
|
|
|
const void *start,
|
|
|
|
size_t size,
|
2022-06-10 10:30:19 +02:00
|
|
|
bool asm_addr,
|
2022-06-16 22:49:27 +02:00
|
|
|
ir_ctx *ctx,
|
2022-05-27 12:18:04 +02:00
|
|
|
FILE *f);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
/* Linux perf interface (implementation in ir_perf.c) */
|
|
|
|
void ir_perf_jitdump_open(void);
|
|
|
|
void ir_perf_jitdump_close(void);
|
|
|
|
void ir_perf_jitdump_register(const char *name, const void *start, size_t size);
|
|
|
|
void ir_perf_map_register(const char *name, const void *start, size_t size);
|
|
|
|
|
|
|
|
/* GDB JIT interface (implementation in ir_gdb.c) */
|
|
|
|
int ir_gdb_register(const char *name,
|
|
|
|
const void *start,
|
|
|
|
size_t size,
|
|
|
|
uint32_t sp_offset,
|
|
|
|
uint32_t sp_adjustment);
|
|
|
|
void ir_gdb_unregister_all(void);
|
|
|
|
bool ir_gdb_present(void);
|
|
|
|
|
|
|
|
/* IR load API (implementation in ir_load.c) */
|
|
|
|
void ir_loader_init(void);
|
|
|
|
void ir_loader_free(void);
|
|
|
|
int ir_load(ir_ctx *ctx, FILE *f);
|
|
|
|
|
|
|
|
/* IR save API (implementation in ir_save.c) */
|
2023-03-28 12:18:12 +02:00
|
|
|
void ir_save(const ir_ctx *ctx, FILE *f);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
/* IR debug dump API (implementation in ir_dump.c) */
|
2023-03-28 12:18:12 +02:00
|
|
|
void ir_dump(const ir_ctx *ctx, FILE *f);
|
|
|
|
void ir_dump_dot(const ir_ctx *ctx, FILE *f);
|
|
|
|
void ir_dump_use_lists(const ir_ctx *ctx, FILE *f);
|
2022-04-05 23:19:23 +02:00
|
|
|
void ir_dump_cfg(ir_ctx *ctx, FILE *f);
|
2023-03-28 12:18:12 +02:00
|
|
|
void ir_dump_cfg_map(const ir_ctx *ctx, FILE *f);
|
|
|
|
void ir_dump_live_ranges(const ir_ctx *ctx, FILE *f);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
/* IR to C conversion (implementation in ir_emit_c.c) */
|
|
|
|
int ir_emit_c(ir_ctx *ctx, FILE *f);
|
|
|
|
|
|
|
|
/* IR verification API (implementation in ir_check.c) */
|
2023-03-28 12:18:12 +02:00
|
|
|
bool ir_check(const ir_ctx *ctx);
|
2022-05-27 12:18:04 +02:00
|
|
|
void ir_consistency_check(void);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-10-26 12:44:44 +02:00
|
|
|
/* Code patching (implementation in ir_patch.c) */
|
|
|
|
int ir_patch(const void *code, size_t size, uint32_t jmp_table_size, const void *from_addr, const void *to_addr);
|
|
|
|
|
2023-04-18 08:54:35 +02:00
|
|
|
/* CPU information (implementation in ir_cpuinfo.c) */
|
|
|
|
#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
|
|
|
|
# define IR_X86_SSE2 (1<<0)
|
|
|
|
# define IR_X86_SSE3 (1<<1)
|
|
|
|
# define IR_X86_SSSE3 (1<<2)
|
|
|
|
# define IR_X86_SSE41 (1<<3)
|
|
|
|
# define IR_X86_SSE42 (1<<4)
|
|
|
|
# define IR_X86_AVX (1<<5)
|
|
|
|
# define IR_X86_AVX2 (1<<6)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
uint32_t ir_cpuinfo(void);
|
|
|
|
|
2022-10-26 14:46:59 +02:00
|
|
|
/* Deoptimization helpers */
|
|
|
|
const void *ir_emit_exitgroup(uint32_t first_exit_point, uint32_t exit_points_per_group, const void *exit_addr, void *code_buffer, size_t code_buffer_size, size_t *size_ptr);
|
2022-10-26 12:44:44 +02:00
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
/* IR Memmory Allocation */
|
2022-08-10 16:41:14 +02:00
|
|
|
#ifndef ir_mem_malloc
|
|
|
|
# define ir_mem_malloc malloc
|
|
|
|
#endif
|
|
|
|
#ifndef ir_mem_calloc
|
|
|
|
# define ir_mem_calloc calloc
|
|
|
|
#endif
|
|
|
|
#ifndef ir_mem_realloc
|
|
|
|
# define ir_mem_realloc realloc
|
|
|
|
#endif
|
|
|
|
#ifndef ir_mem_free
|
|
|
|
# define ir_mem_free free
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef ir_mem_pmalloc
|
|
|
|
# define ir_mem_pmalloc malloc
|
|
|
|
#endif
|
|
|
|
#ifndef ir_mem_pcalloc
|
|
|
|
# define ir_mem_pcalloc calloc
|
|
|
|
#endif
|
|
|
|
#ifndef ir_mem_prealloc
|
|
|
|
# define ir_mem_prealloc realloc
|
|
|
|
#endif
|
|
|
|
#ifndef ir_mem_pfree
|
|
|
|
# define ir_mem_pfree free
|
|
|
|
#endif
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-05-27 12:18:04 +02:00
|
|
|
void *ir_mem_mmap(size_t size);
|
|
|
|
int ir_mem_unmap(void *ptr, size_t size);
|
|
|
|
int ir_mem_protect(void *ptr, size_t size);
|
|
|
|
int ir_mem_unprotect(void *ptr, size_t size);
|
|
|
|
int ir_mem_flush(void *ptr, size_t size);
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2023-03-27 00:29:58 +02:00
|
|
|
#ifdef __cplusplus
|
|
|
|
} /* extern "C" */
|
|
|
|
#endif
|
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
#endif /* IR_H */
|