danog/ir
1
0
Fork 0
mirror of https://github.com/danog/ir.git synced 2024-12-02 09:38:29 +01:00
Code Issues Packages Projects Releases Wiki Activity
1,058 Commits 2 Branches 0 Tags 3.2 MiB
fixup_examples
Commit Graph

174 Commits

Author SHA1 Message Date
Dmitry Stogov
bf856b5e7d Escpae/unescape strings in proper places 2023-12-29 14:37:28 +03:00
Dmitry Stogov
ac695a9acf Imptove support for symbolic constants 2023-12-27 10:18:56 +03:00
Dmitry Stogov
3dd4146097
Allow using "thunks" to call "far" functions (#57) 
* Allow using "thunks" to call "far" functions

* Fix Windows tests

* Fix identation
 2023-12-19 22:22:49 +03:00
Dmitry Stogov
bb739cca9b Don't optimize signed division by power of two 2023-12-15 14:01:46 +03:00
Dmitry Stogov
752379975b Fixed code generation for MAX 2023-12-14 23:35:36 +03:00
Dmitry Stogov
dab739f3d2 Fix Windows tests 2023-12-08 17:46:12 +03:00
Dmitry Stogov
1e8ff8078a Cleanup symbolic constants usage 2023-12-08 17:35:41 +03:00
Dmitry Stogov
6a7a87529c Improve LLVM export (avoid duplicate function declarations) 2023-12-05 23:09:39 +03:00
Dmitry Stogov
76e6418cae Support for function prototypes 2023-11-30 21:10:41 +03:00
Dmitry Stogov
8c501e1989 Fixed VA_ARG support for WIN64 2023-11-23 20:55:10 +03:00
Dmitry Stogov
5bacc13b2c Add VA_ARG tests 2023-11-23 19:45:52 +03:00
Dmitry Stogov
25bd3024da Codegeneration for VA_ARG nodes (Windows and MacOS are not supported yet) 2023-11-23 19:38:33 +03:00
Dmitry Stogov
1d6cf229ef Fix typo 2023-11-22 11:36:30 +03:00
Dmitry Stogov
688f876928 mplemented code-generation for bit counting instructions 2023-11-16 22:48:05 +03:00
Dmitry Stogov
92ef948caf Implemented code-generation for CTPOP 2023-11-16 19:28:12 +03:00
Dmitry Stogov
d5596d815e Stop reporting zero exit code when run JIT-ed code 2023-11-16 13:57:37 +03:00
Dmitry Stogov
1eaf5531e5 Fixed test 2023-11-08 10:20:55 +03:00
Dmitry Stogov
400fa2805d An attempt to fix tests on Windows 2023-10-24 11:12:37 +03:00
Dmitry Stogov
6edb011548 Fixed code generation for unordered floating point comparison 
- Fixed COND on AArch64
- Fixed SYM support on AArch64
 2023-10-24 10:22:04 +03:00
Dmitry Stogov
d60d92516d Fixed tests 2023-10-20 17:50:31 +03:00
Dmitry Stogov
49316643e7 Initial support for modules (incomplete) 2023-10-20 17:44:45 +03:00
Dmitry Stogov
9b1ce974cb Improve loader interface (incomplete) 2023-10-20 01:09:46 +03:00
Dmitry Stogov
4f9724a7fb Fix tests 2023-10-13 21:04:38 +03:00
Dmitry Stogov
66e9693019 Fix tests 2023-10-13 20:57:42 +03:00
Dmitry Stogov
613fca0327 Implemented code generation for COND (not optimized) 2023-10-13 20:50:23 +03:00
Dmitry Stogov
dd227dfa25 New tests 2023-10-12 15:01:27 +03:00
Dmitry Stogov
1970a16496 Fixed crash on dead PHI 2023-10-12 14:54:23 +03:00
Dmitry Stogov
211884cf29 Introduce API to load modules 2023-10-11 22:55:25 +03:00
Javier Eguiluz
2f4f8504d4
Fix some typos (#51) 2023-10-03 08:34:02 +03:00
Dmitry Stogov
9ea551a34f LLVM support for fastcall and vararg 2023-09-29 11:30:53 +03:00
Dmitry Stogov
51a37f159b Initial implementation of LLVM export 2023-09-28 20:44:45 +03:00
Dmitry Stogov
09829a9e69 Fixed x86_64 calling convention for vararg functions 
%al is used as a hidden register to specify the number of passed vector registers
 2023-09-27 10:23:34 +03:00
Dmitry Stogov
399a387713 Avoid MOVD/MOVQ disassemble mismatch with old/new capstone versions 2023-09-19 16:30:09 +03:00
Dmitry Stogov
7650500a7c Remove -nan 2023-09-12 22:15:36 +03:00
Dmitry Stogov
834eb77e90 Fixed support for float, inf and nan constants. 2023-09-12 22:05:11 +03:00
Dmitry Stogov
0dbb794399
CI tests for MACOS build (#46) 2023-08-30 15:24:12 +03:00
Dmitry Stogov
7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
 2023-06-29 12:42:44 +03:00
Dmitry Stogov
2bfe1626ad Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator" 2023-06-28 22:00:50 +03:00
Dmitry Stogov
141d46f5d8 Fixed tests 2023-06-27 11:34:13 +03:00
Dmitry Stogov
8a5a81c03e Improve live interval splitting and eliminate more redundand spill loads 2023-06-27 11:29:26 +03:00
Dmitry Stogov
678a6af863 Eliminate duplicate spill loads at the same basic block 2023-06-22 14:41:01 +03:00
Dmitry Stogov
85beed7901 Fixed incorrect oredering of moves during de-SSA 
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
 2023-06-22 12:07:19 +03:00
Dmitry Stogov
35f94d570f Revert "Eliminate duplicate spill loads at the same basic block" 
This reverts commit 5d05d78462.
 2023-06-22 01:58:26 +03:00
Dmitry Stogov
5d05d78462 Eliminate duplicate spill loads at the same basic block 2023-06-22 01:24:50 +03:00
Dmitry Stogov
ebaefd376a Fix stack frame and assign all spill slots before code genearatin 2023-06-21 19:04:22 +03:00
Dmitry Stogov
ffac404552 Fix impossible load fusion 2023-06-20 12:14:52 +03:00
Dmitry Stogov
009e9c4a53 Split assign_regs() loop into two versions (with and without spilling). 2023-06-20 08:34:54 +03:00
Dmitry Stogov
cc87d1291f Fixed tests 2023-06-09 16:29:38 +03:00
Dmitry Stogov
6a8830c1dc Better usage of the register hints 2023-06-09 16:26:15 +03:00
Dmitry Stogov
0d3af66a2b Fix test 2023-06-09 10:58:49 +03:00