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469 Commits

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Author SHA1 Message Date
Dmitry Stogov
4c536aae20 Extend SCCP to perform Dead Load Elimination 2022-11-08 15:39:00 +03:00
Dmitry Stogov
551ea4d2a0 Fix incorrect RSTORE flags 2022-11-08 15:25:01 +03:00
Dmitry Stogov
37dececa71 Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
Dmitry Stogov
cc56f12f13 Add LICENSE and copyright notices 2022-11-08 11:32:46 +03:00
Dmitry Stogov
2ff0617db6 Perform iterative folding and DCE as a final pass of SCCP 2022-11-08 00:41:08 +03:00
Dmitry Stogov
5ba4050248 cleanup SCCP 2022-11-08 00:37:28 +03:00
Dmitry Stogov
ef6b6c3e26 Prevent CSE for (ADD/SUB/MUL)_OV 2022-11-03 15:58:51 +03:00
Dmitry Stogov
56c22a205f Constant folding for ADD_OV/SUB_OV 2022-11-03 14:30:49 +03:00
Dmitry Stogov
22385c1528 Allocate and reuse spill slots using simple linear-scan (without holes) 2022-11-02 21:53:05 +03:00
Dmitry Stogov
0a5bb4a571 Better condition 2022-11-02 21:28:56 +03:00
Dmitry Stogov
802ec945ad Reorder conditions for the most common case 2022-11-02 16:27:26 +03:00
Dmitry Stogov
364669a0a1 Add/fix comments 2022-11-02 16:27:16 +03:00
Dmitry Stogov
d619efa0ad Add support for ENDBR 2022-10-27 12:58:04 +03:00
Dmitry Stogov
66330273b1 Add "endbr" instruction 2022-10-27 11:13:50 +03:00
Dmitry Stogov
3af9e1a062 Move some common code into ir_emit.c 2022-10-26 22:52:19 +03:00
Dmitry Stogov
1b84570aa3 Intoduce ir_emit.c that shuould keep common part for different targets 2022-10-26 22:06:07 +03:00
Dmitry Stogov
62c981a091 remove hardcoded dependencies 2022-10-26 21:26:24 +03:00
Dmitry Stogov
74debb0bf4 Add "ir_load.c" to allow build without llk.php and initial multi-platform support 2022-10-26 19:52:14 +03:00
Dmitry Stogov
95e6cafe7c cleanup 2022-10-26 16:06:16 +03:00
Dmitry Stogov
9b7835a05e Use ir_emit_exitgroup() helper API instead of IR_EXITGROUP node 2022-10-26 15:46:59 +03:00
Dmitry Stogov
2dea40bfab Add API to patch native code 2022-10-26 13:44:44 +03:00
Dmitry Stogov
edd7bc7101 Access ctx->rules[] trough inline function with assertion 
Fix incorrect accesses
 2022-10-26 12:49:34 +03:00
Dmitry Stogov
b99d98979f Limit CMP+GUARD fusing 2022-10-25 22:09:32 +03:00
Dmitry Stogov
006bee10c7 Add checks for constant references before checking the corresponding rule 2022-10-25 20:36:22 +03:00
Dmitry Stogov
4b114914dc Prevent register clobbering 2022-10-25 12:24:05 +03:00
Dmitry Stogov
ba90e2825e SNAPSHOT data shouldn't be in registers 2022-10-25 12:22:49 +03:00
Dmitry Stogov
265ebc1000 Fix two LSRA edge cases 2022-10-24 21:55:59 +03:00
Dmitry Stogov
9f472c1c91 Add support for deoptimization and binding to multiple slots 2022-10-21 17:16:25 +03:00
Dmitry Stogov
6667b7efae Fix register allocation (one of operands MUST be in a register) 2022-10-21 12:02:31 +03:00
Dmitry Stogov
22cd9265d3 Check if the register is necessary at all 2022-10-18 22:02:09 +03:00
Dmitry Stogov
1dcfe127e1 Allow save/load "null" references 2022-10-18 15:52:25 +03:00
Dmitry Stogov
3d175e1576 Fix fuse load 2022-10-18 13:53:00 +03:00
Dmitry Stogov
ecb9719e8b Fix "long" PHI handling 2022-10-12 14:01:56 +03:00
Dmitry Stogov
81c90972d6 Avoid useless spill stores 2022-10-12 12:09:52 +03:00
Dmitry Stogov
678da7fcc1 Use proper MOV instructions 2022-10-12 12:01:49 +03:00
Dmitry Stogov
6e0415a44d Fix SCCP for PHIs 2022-10-12 12:01:28 +03:00
Dmitry Stogov
c74cac2556 Fix support for "long" PHIs 2022-10-12 11:59:49 +03:00
Dmitry Stogov
3ef58e5c2e Take into account RLOADs for non fixed registers 2022-10-11 22:23:09 +03:00
Dmitry Stogov
f5c0151740 Remove hints to the same virtual register 2022-10-05 20:31:20 +03:00
Dmitry Stogov
e9402c8436 Add hint for "op1" if result reuses "op1" register. 
This improves register allocation if regiter for result was coalesced and allocated before the register for operand.
 2022-10-05 17:58:37 +03:00
Dmitry Stogov
d2a0347b21 Merge basic blocks by removing connected END to BEGIN nodes 2022-10-05 16:29:49 +03:00
Dmitry Stogov
db8a80e8d5 Temporary remove "pxor". 
It should be added before all "cvt*" instructions
 2022-09-29 20:05:00 +03:00
Dmitry Stogov
a98124a552 External __jit_debug_register_code() is necessary only on ARM 2022-09-29 17:10:32 +03:00
Dmitry Stogov
0da4b43de8 Fix second argument address 2022-09-29 14:17:54 +03:00
Dmitry Stogov
33bc4ce956 Fixed comparison with zero 2022-09-29 11:31:07 +03:00
Dmitry Stogov
a6e4e988d0 Fix ARM code generator 2022-09-29 02:10:44 +03:00
Dmitry Stogov
c3e6a71dda Allow using external __jit_debug_register_code(). 
Fuinction defined in DSO may work improperly.
 2022-09-29 01:28:30 +03:00
Dmitry Stogov
494c9225a9 Refactor trace related helpers 2022-09-29 01:25:42 +03:00
Dmitry Stogov
81f1108049 Add task 2022-09-28 21:58:38 +03:00
Dmitry Stogov
fdaa0cea54 Ignore dead TLS loads 2022-09-28 21:56:10 +03:00