Dmitry Stogov
|
8895b18c0c
|
Added task
|
2022-05-13 09:06:43 +03:00 |
|
Dmitry Stogov
|
cd6eb1354a
|
Renumber virtual registers
|
2022-05-13 01:15:24 +03:00 |
|
Dmitry Stogov
|
1f673ebfda
|
Better temporary register usage for SSA deconstruction
|
2022-05-13 00:32:37 +03:00 |
|
Dmitry Stogov
|
cd00ae6099
|
Allow spill slot fusing when swap operands of fp comparison
|
2022-05-12 21:58:58 +03:00 |
|
Dmitry Stogov
|
386b140265
|
Refactor Linear Scan Register Allocator to use linked lists instead of bitsets
This fixes allocation of several temporary variables for single instruction
|
2022-05-12 17:43:08 +03:00 |
|
Dmitry Stogov
|
1028d7d330
|
Fix reading behind array range
|
2022-05-12 11:04:20 +03:00 |
|
Dmitry Stogov
|
d3c4844da7
|
Fix reading behind array range
|
2022-05-12 10:57:38 +03:00 |
|
Dmitry Stogov
|
c2d224148b
|
Use prefered register if possible
|
2022-05-11 21:10:35 +03:00 |
|
Dmitry Stogov
|
f8edcb9762
|
Fix possible crash
|
2022-05-11 18:18:28 +03:00 |
|
Dmitry Stogov
|
6d7ea2fd37
|
Prevent crash when dump dessa moves with -O0
|
2022-05-11 17:05:29 +03:00 |
|
Dmitry Stogov
|
4569d80218
|
Remove temporary test files
|
2022-05-06 19:19:04 +03:00 |
|
Dmitry Stogov
|
2580813c48
|
cleanup
|
2022-05-06 19:05:39 +03:00 |
|
Dmitry Stogov
|
69b5a852e5
|
Make DESSA API use "ir_ref" instead of "virtual register number"
(0 - is still a temporary register)
|
2022-05-06 16:19:57 +03:00 |
|
Dmitry Stogov
|
b2033ebaf9
|
Fixed parallel copy
|
2022-05-06 13:32:20 +03:00 |
|
Dmitry Stogov
|
b6ce5055e1
|
Fix register usage in CALL
|
2022-05-06 13:12:19 +03:00 |
|
Dmitry Stogov
|
2403fa1edc
|
Fix spill loads during argument passing
|
2022-05-06 12:55:07 +03:00 |
|
Dmitry Stogov
|
b580c926e6
|
Avoid need for temporary register for parameters loading
|
2022-05-06 11:27:24 +03:00 |
|
Dmitry Stogov
|
e434c0a8aa
|
Cleanup and add asserion for unimplemented case
|
2022-05-06 11:10:09 +03:00 |
|
Dmitry Stogov
|
9d51134813
|
cleanup
|
2022-05-06 10:37:25 +03:00 |
|
Dmitry Stogov
|
89f320d7b7
|
Add SWITCH support for temporary registers
|
2022-05-06 10:00:19 +03:00 |
|
Dmitry Stogov
|
9f1ca6b82c
|
Add IR_LIVE_INTERVAL_TEMP and IR_LIVE_INTERVAL_VAR flags
|
2022-05-06 09:23:14 +03:00 |
|
Dmitry Stogov
|
048ff19133
|
cleanup
|
2022-05-05 23:43:16 +03:00 |
|
Dmitry Stogov
|
3c6e4c8b3a
|
Use -O2 for release build
|
2022-05-05 22:37:25 +03:00 |
|
Dmitry Stogov
|
dd5a3a3b72
|
Add flexible support for temporary registers.
Get rid of hardcoded temporary registers (incomplete)
|
2022-05-05 22:35:39 +03:00 |
|
Dmitry Stogov
|
7de4566498
|
Add tests for 64-bit constants
|
2022-05-04 15:37:07 +03:00 |
|
Dmitry Stogov
|
1130c256ae
|
Find optimal split position
|
2022-05-04 11:59:35 +03:00 |
|
Dmitry Stogov
|
4f294109e8
|
Result of PARAM may be stored into a spill slot without register
|
2022-05-04 09:50:23 +03:00 |
|
Dmitry Stogov
|
a5b676b590
|
Fix incorrect operands order
|
2022-05-04 09:11:05 +03:00 |
|
Dmitry Stogov
|
1b156c49e8
|
Use "hint" regiser only if it's not disabled by "--debug-regset"
|
2022-05-04 09:08:23 +03:00 |
|
Dmitry Stogov
|
27540fd43a
|
Use optimal split position (incompete)
|
2022-04-29 19:24:15 +03:00 |
|
Dmitry Stogov
|
b3c61507a4
|
Fixed possible incorrect splitting
|
2022-04-29 18:50:57 +03:00 |
|
Dmitry Stogov
|
102b367d64
|
cleanup
|
2022-04-29 15:24:41 +03:00 |
|
Dmitry Stogov
|
f5f9614854
|
cleanup
|
2022-04-29 14:19:53 +03:00 |
|
Dmitry Stogov
|
23945c4bdc
|
Better debug logging
|
2022-04-29 12:14:26 +03:00 |
|
Dmitry Stogov
|
2e3ba321f8
|
Swap UsePos flags and prefer to reload registers that SHOULD be in a CPU register
|
2022-04-29 03:39:32 +03:00 |
|
Dmitry Stogov
|
3e6f84eef4
|
Add "must be in reg" constraint
|
2022-04-28 14:48:43 +03:00 |
|
Dmitry Stogov
|
ea46798aeb
|
Fix live interval splitting and second chance binpacking (it seems to work, but may be icomplete)
|
2022-04-28 13:09:55 +03:00 |
|
Dmitry Stogov
|
acffada3b1
|
Fix interval processing order
|
2022-04-28 10:27:01 +03:00 |
|
Dmitry Stogov
|
fffc0ad2ef
|
Delay spill slot allocation
|
2022-04-28 10:16:02 +03:00 |
|
Dmitry Stogov
|
240259adf8
|
add task
|
2022-04-28 09:23:02 +03:00 |
|
Dmitry Stogov
|
53532fcb39
|
Select better register
|
2022-04-28 01:25:10 +03:00 |
|
Dmitry Stogov
|
5b7a7decd0
|
Fix splitting of use positions
|
2022-04-28 00:12:01 +03:00 |
|
Dmitry Stogov
|
9287830a77
|
Process remaining splits after all unhandled intervals
|
2022-04-27 23:31:20 +03:00 |
|
Dmitry Stogov
|
59b63cbb91
|
Sort oputput UsePos after inputs
|
2022-04-27 21:24:51 +03:00 |
|
Dmitry Stogov
|
7f8f186abd
|
Fix the way as linera-scan walks through splitted intervals
|
2022-04-27 18:18:53 +03:00 |
|
Dmitry Stogov
|
6e77f886cb
|
LSRA tweaks
|
2022-04-27 15:02:51 +03:00 |
|
Dmitry Stogov
|
2b9e793b4e
|
Add debug options
|
2022-04-27 14:47:52 +03:00 |
|
Dmitry Stogov
|
c89246f35a
|
Replace asserts with checks
|
2022-04-27 01:34:29 +03:00 |
|
Dmitry Stogov
|
329e1f5a44
|
Fix splitting (incomplete)
|
2022-04-27 01:04:03 +03:00 |
|
Dmitry Stogov
|
310f605d6c
|
Fix register clobbering
|
2022-04-26 22:49:41 +03:00 |
|