Anatol Belski
964f5a0191
build: MSVC compatibility
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Signed-off-by: Anatol Belski <ab@php.net>
2023-02-25 00:04:57 +01:00
Anatol Belski
39c658b5d5
gitignore: Extend with some win32/ paths
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Signed-off-by: Anatol Belski <ab@php.net>
2023-02-24 22:17:36 +01:00
Anatol Belski
ec11fc119b
build: Add MSVC Makefile
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Signed-off-by: Anatol Belski <ab@php.net>
2023-02-24 22:17:35 +01:00
Anatol Belski
e5c1a78746
ci: Extend with MSVC pass
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Signed-off-by: Anatol Belski <ab@php.net>
2023-02-24 22:09:25 +01:00
Dmitry Stogov
c71bcb756a
Fix macro
2023-02-24 17:06:19 +03:00
Dmitry Stogov
00d5e471ad
Improve load fusion, register allocateion and code selection for ADD
2023-02-21 22:55:47 +03:00
Dmitry Stogov
8b4678a9ae
Add "--dump-size" option
2023-02-21 22:22:41 +03:00
Dmitry Stogov
637fe28e90
Add comments
2023-02-21 15:41:41 +03:00
Dmitry Stogov
9f81982d86
Fix 'mov' to/from 'sp' register
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sp is shared with zero register and 'mov' for sp/xzr is encoded differently
2023-02-21 11:42:05 +03:00
Dmitry Stogov
ab50cc3f05
Merge pull request #7 from arnaud-lb/fix-ir-store-int-tmp-reg
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Fix temporary register allocation for IR_STORE_INT
2023-02-20 10:00:15 +03:00
Arnaud Le Blanc
e95cdd0722
Fix temporary register allocation for IR_STORE_INT
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ir_get_target_constraints() mistakenly tests the instruction type and value
instead of the operands'.
2023-02-18 13:18:49 +01:00
Dmitry Stogov
2f2fed89bb
Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32")
2023-02-17 18:11:13 +03:00
Dmitry Stogov
c71076d3f0
Allow reservation stack for passing arguments
2023-02-17 15:52:26 +03:00
Dmitry Stogov
2bf6334f69
Remove "usafe" non-typed IR builder macros
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Usages of ctx->ir_base[] is not safe, because the array may be reallocated by any ir_emit/ir_fold call.
2023-02-17 13:20:39 +03:00
Dmitry Stogov
28a5714a8e
Use ANSI symbols
2023-02-17 09:11:38 +03:00
Dmitry Stogov
fd653528e9
JMP optimization. Lift constant IJMP targets into jmp_table(s).
2023-02-16 22:41:55 +03:00
Dmitry Stogov
31ea3153f3
Add (commeted) code that could eliminate register move for RSTORE
2023-02-16 17:49:30 +03:00
Dmitry Stogov
ec8489bf6f
Fix spill load
2023-02-16 01:46:16 +03:00
Dmitry Stogov
c7e2cca534
Add hint to reuse register in ZEXT/SEXT
2023-02-15 18:33:02 +03:00
Dmitry Stogov
d07a2db592
Improve GCM to schedule floating nodes that depends only on constants
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(e.g. COPY(CONST)) to the last common ancestor.
Previously these nodes went to the first block.
2023-02-15 15:18:42 +03:00
Dmitry Stogov
1d7ab16c2a
Allow load fuson for CALL and TAILCALL with arguments
2023-02-14 14:51:12 +03:00
Dmitry Stogov
36553fdf14
Fix merging of empty ENTRY block with its successor
2023-02-14 14:07:54 +03:00
Dmitry Stogov
a02f39435a
Merge pull request #4 from weltling/makefile_simplify
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makefile: Simplify and regroup objects and targets
2023-02-14 12:16:46 +03:00
Dmitry Stogov
320845fcf9
Update the picture
2023-02-14 11:52:50 +03:00
Dmitry Stogov
e19ecd94c3
Eliminate unnecessary "test" or comparison instruction for IF(CMP_OP(BIN_OP(_, _), 0))
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TODO: this should be ported to ARM
2023-02-14 11:25:16 +03:00
Anatol Belski
7b3dc08b05
makefile: Simplify and regroup objects and targets
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A small optimization to combine common pieces in the makefile.
- Use static pattern rules for the same operation
- Group headers prerequisities into own targets
- Reduce dups like objects to be listed just once in a var, etc.
Signed-off-by: Anatol Belski <ab@php.net>
2023-02-14 00:23:45 +01:00
Dmitry Stogov
d19685375c
Add few missing IR builder macros
2023-02-13 20:55:54 +03:00
Dmitry Stogov
a96defc13b
Fix ir_TLS() macro
2023-02-13 20:26:36 +03:00
Dmitry Stogov
ab994122e7
Merge pull request #6 from nielsdos/fix-use-list
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Fix SCCP use list update for op3
2023-02-13 09:37:52 +03:00
Dmitry Stogov
df8bf5cc5a
Merge pull request #5 from nielsdos/fix-i64-check
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Fix incorrect val.i64 check
2023-02-13 09:32:07 +03:00
Niels Dossche
1e772c500e
Fix SCCP use list update for op3
2023-02-12 14:18:17 +01:00
Niels Dossche
9d3354e89e
Fix incorrect val.i64 check
2023-02-12 14:11:31 +01:00
Dmitry Stogov
6b8a33d726
Introduce IR Builder API
2023-02-10 13:34:46 +03:00
Dmitry Stogov
9b6b6996c4
Move IR_ALWAYS_INLINE and IR_NEVER_INLINE definition into public ir.h
2023-02-07 23:14:10 +03:00
Dmitry Stogov
6a4187eacc
Fixed CLANG build
2023-02-07 23:11:16 +03:00
Dmitry Stogov
d7ed2fdfad
We can't relay on block order because they are re-scheduled later
2023-02-07 03:30:44 +03:00
Dmitry Stogov
2e31446e37
Better 'jp' elimination for IR_CMP_AND_BRANCH_FP
2023-02-07 01:57:07 +03:00
Dmitry Stogov
6521c0b7e4
Better 'jp' elimination for GUARDs
2023-02-07 01:06:30 +03:00
Dmitry Stogov
02104b0950
Add XFAIL-ed test for a non-efficient register allocation that should be improved
2023-02-07 00:06:53 +03:00
Dmitry Stogov
aada927840
Add type checks for LOAD/STORE and VLOAD/VSTORE
2023-02-07 00:05:59 +03:00
Dmitry Stogov
1773bb81aa
Make a decision about load fusion and operand swapping together
2023-02-05 14:48:14 +03:00
Dmitry Stogov
cfc959d8ca
Better load fusion
2023-02-03 12:50:00 +03:00
Dmitry Stogov
dc728853a2
JMP optimization for GUARDs (guard failur is unexpected)
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TODO: this should be ported to ARM
2023-02-01 14:51:36 +03:00
Dmitry Stogov
743696fe03
Simplify condition
2023-01-31 16:15:08 +03:00
Dmitry Stogov
038b1e43cd
We can't preallocate stack for fastcall function calls
2023-01-31 16:13:15 +03:00
Dmitry Stogov
58ba18bb7d
Fix ir_test and set proper initial SP offset info for GDB backtraces
2023-01-31 11:51:55 +03:00
Dmitry Stogov
677c6cb2cb
Move declaration of some register alloation related macros to public API
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Use RLOAD.op3 as a flag to avoid spill store
2023-01-30 16:33:57 +03:00
Dmitry Stogov
bbfcb3e8c8
Fix register allocation for MUL_OV in a different way
2023-01-26 13:20:08 +03:00
Dmitry Stogov
4fb50d85aa
Add assertion when allocated preserved register is not saved in "fixed" frame prologue
2023-01-26 12:49:23 +03:00
Dmitry Stogov
761c50488e
Fix incorrect code generation
2023-01-26 11:50:10 +03:00
