Dmitry Stogov
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a25f85e5dd
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Fix support for difference in qsort_r/s() on Windows, MAC and GNU
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2023-08-30 02:35:06 +03:00 |
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Dmitry Stogov
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439f202aed
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Support for difference in qsort_r() on MAC and GNU
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2023-08-30 00:52:24 +03:00 |
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Dmitry Stogov
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bacd55fbda
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Fix compilation warning
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2023-08-30 00:28:33 +03:00 |
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Dmitry Stogov
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dd2ecad299
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Allow reuse of spill slots for objecs of smaller size
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2023-08-02 13:20:13 +03:00 |
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Dmitry Stogov
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283f1a3a13
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Avoid generation of dead PHI
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2023-08-01 14:43:57 +03:00 |
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Dmitry Stogov
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9df73782ed
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Fixed support for fake contol edges between END and ENTRY
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2023-08-01 13:07:49 +03:00 |
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Dmitry Stogov
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1d49fe6cc4
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Reduce cost of disabled IR_ASSERT()
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2023-07-27 11:16:00 +03:00 |
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Dmitry Stogov
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c2a53d29fa
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Rearrange code for better performance
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2023-07-26 22:32:14 +03:00 |
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Dmitry Stogov
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0f12ea8c71
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Add comments for expanded DynASM macros
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2023-07-26 22:05:01 +03:00 |
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Dmitry Stogov
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e60bb978f4
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Use _xlat[] slots for "used constants" markers
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2023-07-07 13:57:01 +03:00 |
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Dmitry Stogov
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4bb03ab7e3
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ws
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2023-07-07 11:53:11 +03:00 |
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Dmitry Stogov
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5b90420b18
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Improved unused constant elimination
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2023-07-07 11:15:52 +03:00 |
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Dmitry Stogov
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496a98708e
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Improved IR linearization
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2023-07-07 02:11:03 +03:00 |
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Dmitry Stogov
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ef201cd349
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Use xlat[] directly (instead of "scheduled" bitset).
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2023-07-06 19:34:20 +03:00 |
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Dmitry Stogov
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78c377ed2d
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Store negarive block number in schedule_early() and postive in
schedule_late(). This eliminates a need for "visited" bitset.
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2023-07-06 19:30:56 +03:00 |
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Dmitry Stogov
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d41abefd58
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Move processing of the last node of the block out of the loop
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2023-07-06 14:10:50 +03:00 |
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Dmitry Stogov
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59dbef0cfb
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typo
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2023-07-06 12:59:33 +03:00 |
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Dmitry Stogov
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f6cf9140da
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Update ir_insn.inputs_count and use it after ir_build_def_use_lists()
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2023-07-06 01:15:08 +03:00 |
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Dmitry Stogov
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d7d7d5fc1b
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Implemented a faster ir_build_def_use_lists() with higher temporary memory requirement
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2023-07-05 16:44:09 +03:00 |
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Dmitry Stogov
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8c331e3264
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typo
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2023-07-04 18:22:15 +03:00 |
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Dmitry Stogov
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da9c406cf5
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Always build ir_ctx.cfg_map during scheduling (it's used for spill code placement)
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2023-07-04 16:37:21 +03:00 |
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Dmitry Stogov
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19e08d42e9
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Cleanup
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2023-07-04 15:19:35 +03:00 |
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Dmitry Stogov
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ea7b921f1b
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Cleanup
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2023-07-04 12:19:24 +03:00 |
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Dmitry Stogov
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c52fa3e6e0
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Clenaup and new folding rules
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2023-07-04 12:15:38 +03:00 |
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Dmitry Stogov
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444806bd72
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Fix Makefile
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2023-07-04 10:36:15 +03:00 |
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Dmitry Stogov
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cf28a299cd
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Fix Makefile dependencies
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2023-07-04 10:03:33 +03:00 |
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Dmitry Stogov
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72a8fcf0f5
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typo
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2023-07-04 09:23:08 +03:00 |
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Dmitry Stogov
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5eb09ce7a5
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Add comments
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2023-07-04 09:22:28 +03:00 |
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Dmitry Stogov
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51d1bbbe09
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Merge pull request #45 from weltling/example_func_call
examples: Add native function call example
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2023-07-03 09:37:56 +03:00 |
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Anatol Belski
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c437cc6df6
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examples: Add native function call example
Signed-off-by: Anatol Belski <anbelski@linux.microsoft.com>
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2023-07-02 18:41:43 +02:00 |
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Dmitry Stogov
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ce2d6ceba6
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Fixed non-boolean constant GUARD condition checks
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2023-06-29 23:49:20 +03:00 |
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Dmitry Stogov
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7058c41411
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More accurate spill loads optimization for instructions that reuse op1 register for result
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
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2023-06-29 12:42:44 +03:00 |
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Dmitry Stogov
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865daeb988
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Duxed support for multi-word instructions
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2023-06-29 00:29:18 +03:00 |
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Dmitry Stogov
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2bfe1626ad
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Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator"
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2023-06-28 22:00:50 +03:00 |
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Dmitry Stogov
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b1e6ae66e3
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More accurate reslution of a register allocation conflict
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2023-06-28 16:17:21 +03:00 |
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Dmitry Stogov
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1b88d998c8
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Fixed inactive interval splitting
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2023-06-27 15:48:35 +03:00 |
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Dmitry Stogov
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b9fc218604
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Remove first part of splitted inactive interval from the "inactive" list
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2023-06-27 15:04:10 +03:00 |
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Dmitry Stogov
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141d46f5d8
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Fixed tests
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2023-06-27 11:34:13 +03:00 |
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Dmitry Stogov
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8a5a81c03e
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Improve live interval splitting and eliminate more redundand spill loads
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2023-06-27 11:29:26 +03:00 |
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Dmitry Stogov
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9cec28c188
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Fixed compilation warnings
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2023-06-22 14:50:14 +03:00 |
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Dmitry Stogov
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678a6af863
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 14:41:01 +03:00 |
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Dmitry Stogov
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85beed7901
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Fixed incorrect oredering of moves during de-SSA
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
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2023-06-22 12:07:19 +03:00 |
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Dmitry Stogov
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35f94d570f
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Revert "Eliminate duplicate spill loads at the same basic block"
This reverts commit 5d05d78462.
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2023-06-22 01:58:26 +03:00 |
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Dmitry Stogov
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5d05d78462
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 01:24:50 +03:00 |
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Dmitry Stogov
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bfb527509d
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Fixed incorrect operands order
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2023-06-21 23:56:47 +03:00 |
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Dmitry Stogov
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99bcde9e1e
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Cleanup spill related code
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2023-06-21 23:20:58 +03:00 |
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Dmitry Stogov
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d67c212916
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Separate codegen info output into ir_dump_codegen()
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2023-06-21 22:36:36 +03:00 |
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Dmitry Stogov
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ebaefd376a
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Fix stack frame and assign all spill slots before code genearatin
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2023-06-21 19:04:22 +03:00 |
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Dmitry Stogov
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4124ef5150
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Allow printing IR annotated with register-allocation, spill-code-placement, de-SSA and code-generation information
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2023-06-21 13:28:15 +03:00 |
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Dmitry Stogov
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25656607ba
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Variabls with a register constraint may be loaed/stored directly from/to a spill slot (without an additional register)
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2023-06-21 01:14:31 +03:00 |
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