Dmitry Stogov
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c28fe2734d
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Validate operand types
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2022-06-03 11:23:05 +03:00 |
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Dmitry Stogov
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30e11861dd
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Aarch64 back-end (incomplete)
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2022-06-03 00:38:49 +03:00 |
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Dmitry Stogov
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fb998c9058
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Aarch64 back-end (incomplete)
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2022-06-02 18:34:47 +03:00 |
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Dmitry Stogov
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2af3f0569d
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Merge last changes from LuaJIT repo
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2022-06-02 15:26:58 +03:00 |
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Dmitry Stogov
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ab8019e0cd
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Aarch64 back-end (incomplete)
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2022-06-02 15:12:56 +03:00 |
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Dmitry Stogov
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77e5e4a62c
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DynAsm/ARM64: Temporary fix for "LSL Rx(dst), Rd(src), #imm" encoding
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2022-06-02 13:40:50 +03:00 |
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Dmitry Stogov
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bb842b489c
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Aarch64 backend support & unification
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2022-06-01 18:16:32 +03:00 |
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Dmitry Stogov
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1be868c779
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Start Aarch64 back-end
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2022-06-01 00:51:02 +03:00 |
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Dmitry Stogov
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91bddc09ed
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Cleanup & unification
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2022-06-01 00:34:45 +03:00 |
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Dmitry Stogov
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00c300fc9f
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Start Aarch64 back-end
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2022-05-31 11:22:31 +03:00 |
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Dmitry Stogov
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a45d40277c
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Replace xmm(dst-IR_REG_XMM0) by xmm(dst-IR_REG_FP_FIRST)
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2022-05-31 10:44:10 +03:00 |
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Dmitry Stogov
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ad8248af31
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Cleanup
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2022-05-31 00:23:04 +03:00 |
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Dmitry Stogov
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41f3e43cf7
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cleanup
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2022-05-27 13:18:04 +03:00 |
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Dmitry Stogov
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3e1816a71f
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Fix register allocation for ABS_INT
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2022-05-27 00:11:31 +03:00 |
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Dmitry Stogov
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2840227291
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Fixed assertion
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2022-05-26 21:44:36 +03:00 |
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Dmitry Stogov
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8683331d60
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Update tasks
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2022-05-26 21:19:42 +03:00 |
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Dmitry Stogov
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77f7d7e2af
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SWITCH elated fixes
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2022-05-26 20:58:07 +03:00 |
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Dmitry Stogov
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4a39bda507
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Fix double passing in 32-bit x86
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2022-05-26 18:26:37 +03:00 |
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Dmitry Stogov
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4974c301bc
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Fix code generation for preserved registers and dessa moves
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2022-05-26 18:08:39 +03:00 |
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Dmitry Stogov
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f5bbdeea27
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Fix buffer overflow
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2022-05-26 17:19:43 +03:00 |
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Dmitry Stogov
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62d7fa7147
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Fix string argument passing
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2022-05-26 16:34:01 +03:00 |
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Dmitry Stogov
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0eef46493e
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Improve code generation
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2022-05-26 16:01:29 +03:00 |
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Dmitry Stogov
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8aac74dfb7
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Improve code generation
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2022-05-26 15:52:42 +03:00 |
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Dmitry Stogov
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2917dbbd59
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Fix register clobbering
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2022-05-26 15:26:04 +03:00 |
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Dmitry Stogov
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4862d69609
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Improve code generation by load fusing
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2022-05-26 14:43:19 +03:00 |
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Dmitry Stogov
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4598bd5b12
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Better 32/64-bit assertions
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2022-05-26 13:37:15 +03:00 |
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Dmitry Stogov
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e9fe55faa0
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Fix param spill-slot assignment in 32-bit back-end
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2022-05-26 13:09:20 +03:00 |
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Dmitry Stogov
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e28a3c801e
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Fix retutn FP numbers for 32-bit x86 back-end
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2022-05-26 11:58:51 +03:00 |
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Dmitry Stogov
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7e782a291a
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Extend disassembler to support .rodata section and IP relative data labels
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2022-05-26 01:17:02 +03:00 |
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Dmitry Stogov
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ead2b69fc6
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x86_32 backend (incomplete)
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2022-05-25 22:00:18 +03:00 |
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Dmitry Stogov
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19e93fd3f6
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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Dmitry Stogov
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235c1f2d65
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Fix stack parameter loading for x86_32
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2022-05-25 15:53:21 +03:00 |
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Dmitry Stogov
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341e3b8083
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Initial support for x86_32 backend (incomplete)
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2022-05-25 14:58:39 +03:00 |
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Dmitry Stogov
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4747a22474
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Update tasks
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2022-05-25 12:04:33 +03:00 |
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Dmitry Stogov
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ac65d71964
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ws
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2022-05-25 12:02:31 +03:00 |
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Dmitry Stogov
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9215162833
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Ger rid of ir_ctx.bb_num and double neaning of ir_ctx.prev_insn_len
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2022-05-25 11:58:35 +03:00 |
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Dmitry Stogov
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740cac8e2f
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Move ir_ctx.unused_live_ranges to local variable
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2022-05-25 10:57:21 +03:00 |
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Dmitry Stogov
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ab220de623
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Fitsr and last instructions of BB and leading PARAM, PHI, PI, VAR instructions don't need to be scheduled.
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2022-05-25 09:43:53 +03:00 |
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Dmitry Stogov
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463002107a
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Rename "gcm_blocks" into "cfg_map"
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2022-05-25 09:33:47 +03:00 |
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Dmitry Stogov
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87e9780a5b
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Fixed handling of constant references
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2022-05-25 09:30:26 +03:00 |
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Dmitry Stogov
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58b67fec18
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Topological sort of nodes in each basic block
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2022-05-24 18:04:38 +03:00 |
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Dmitry Stogov
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ddd5b739db
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Update tasks
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2022-05-24 12:59:57 +03:00 |
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Dmitry Stogov
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04667faf22
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Reorder blocks according to branch probability
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2022-05-24 12:47:39 +03:00 |
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Dmitry Stogov
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d3c1e4a02f
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Reorder basic blocks to reduce number of jumps and improve code locality
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2022-05-24 00:43:35 +03:00 |
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Dmitry Stogov
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596f03f263
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Update tasks
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2022-05-23 19:34:09 +03:00 |
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Dmitry Stogov
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fa36dbf9af
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Update tasks
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2022-05-20 13:09:41 +03:00 |
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Dmitry Stogov
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6f7f7b1268
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Implement code generation for type conversion instructions
Register constraints might need to be tweeked.
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2022-05-20 13:07:41 +03:00 |
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Dmitry Stogov
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c464b123cb
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Add test for TRUNC
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2022-05-20 09:09:52 +03:00 |
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Dmitry Stogov
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d250f77713
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Improve type conversion nodes
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2022-05-20 09:00:13 +03:00 |
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Dmitry Stogov
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c6b0e95d6b
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Add type conversion nodes (no code generation yet)
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2022-05-20 01:01:48 +03:00 |
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