11 Commits

Author	SHA1	Message	Date
Dmitry Stogov	7058c41411	More accurate spill loads optimization for instructions that reuse op1 register for result ... This also fixes possbile incorrect register-allocation/code-generation for SHIFT instuction on x86[_64]	2023-06-29 12:42:44 +03:00
Dmitry Stogov	6a8830c1dc	Better usage of the register hints	2023-06-09 16:26:15 +03:00
Dmitry Stogov	b8be0b9dd9	Avoid loading of stack parameter to register if this is not necessary	2023-06-09 00:35:15 +03:00
Dmitry Stogov	e4b618ad00	Fix fusion of IF(_, CMP(AND(_, _) 0))	2023-03-28 19:03:06 +03:00
Dmitry Stogov	00d5e471ad	Improve load fusion, register allocateion and code selection for ADD	2023-02-21 22:55:47 +03:00
Dmitry Stogov	54597bc862	Clear destination regeister before INT to FP conversion to avoid partial register stall	2022-12-28 00:05:23 +03:00
Dmitry Stogov	95729f76bf	Use IMUL instead of MUL	2022-12-16 12:57:40 +03:00
Dmitry Stogov	daf659a457	Fix incorrect conditions	2022-12-01 00:43:42 +03:00
Dmitry Stogov	c6aeb417fa	Extend test suite to support XFAIL section	2022-11-22 10:43:29 +03:00
Dmitry Stogov	05127b1b13	Remove duplicate code and allow load fusion of IR_SHIFT.op2	2022-11-16 13:20:58 +03:00
Dmitry Stogov	37dececa71	Add more tests (8 tests ara failed on 32-bit x86)	2022-11-08 11:56:22 +03:00