Dmitry Stogov
72a8fcf0f5
typo
2023-07-04 09:23:08 +03:00
Dmitry Stogov
5eb09ce7a5
Add comments
2023-07-04 09:22:28 +03:00
Dmitry Stogov
7058c41411
More accurate spill loads optimization for instructions that reuse op1 register for result
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This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
2023-06-29 12:42:44 +03:00
Dmitry Stogov
865daeb988
Duxed support for multi-word instructions
2023-06-29 00:29:18 +03:00
Dmitry Stogov
2bfe1626ad
Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator"
2023-06-28 22:00:50 +03:00
Dmitry Stogov
b1e6ae66e3
More accurate reslution of a register allocation conflict
2023-06-28 16:17:21 +03:00
Dmitry Stogov
1b88d998c8
Fixed inactive interval splitting
2023-06-27 15:48:35 +03:00
Dmitry Stogov
b9fc218604
Remove first part of splitted inactive interval from the "inactive" list
2023-06-27 15:04:10 +03:00
Dmitry Stogov
8a5a81c03e
Improve live interval splitting and eliminate more redundand spill loads
2023-06-27 11:29:26 +03:00
Dmitry Stogov
678a6af863
Eliminate duplicate spill loads at the same basic block
2023-06-22 14:41:01 +03:00
Dmitry Stogov
35f94d570f
Revert "Eliminate duplicate spill loads at the same basic block"
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This reverts commit 5d05d78462
2023-06-22 01:58:26 +03:00
Dmitry Stogov
5d05d78462
Eliminate duplicate spill loads at the same basic block
2023-06-22 01:24:50 +03:00
Dmitry Stogov
ebaefd376a
Fix stack frame and assign all spill slots before code genearatin
2023-06-21 19:04:22 +03:00
Dmitry Stogov
009e9c4a53
Split assign_regs() loop into two versions (with and without spilling).
2023-06-20 08:34:54 +03:00
Dmitry Stogov
b37d4e0443
Allow usage of CPU stack slots for deoptimization
2023-06-16 02:14:02 +03:00
Dmitry Stogov
6a98514bdc
Move stack size related metricks to ir_ctx
2023-06-15 19:28:54 +03:00
Dmitry Stogov
311267714e
Use macros insted of bit ops
2023-06-14 20:23:32 +03:00
Dmitry Stogov
6a8830c1dc
Better usage of the register hints
2023-06-09 16:26:15 +03:00
Dmitry Stogov
b8be0b9dd9
Avoid loading of stack parameter to register if this is not necessary
2023-06-09 00:35:15 +03:00
Dmitry Stogov
c599cfbdf3
Fixed spill slot allocation
2023-06-07 18:37:37 +03:00
Dmitry Stogov
186dc6b0a6
Fixed GH issue #33 : IR program failed to compile with "-O0" "-S" options
2023-06-05 18:22:12 +03:00
Dmitry Stogov
3b0de17cdd
Added missing fixed interval
2023-06-01 11:00:39 +03:00
Dmitry Stogov
6009e376b7
Speed-up liner scan
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- Don't add allocated interval into "active" list, if it doesn't overlap
with next unhandled
- More efficient selection of registers available for the whole range
2023-06-01 00:48:21 +03:00
Dmitry Stogov
d3640495a2
Ceanup ir_compute_live_ranges() implementation
2023-05-19 12:34:54 +03:00
Dmitry Stogov
5c2023fd7f
Avoid live range constrction for VARs
2023-05-18 21:00:57 +03:00
Dmitry Stogov
ef31712f26
Remove usused IR_LIVE_INTERVAL_REG_LOAD flag
2023-05-18 14:17:54 +03:00
Dmitry Stogov
477dbf7d76
Avoid live range constrction for RLOAD with fixed registers
2023-05-18 13:37:12 +03:00
Dmitry Stogov
b6517f2028
Split IR_LIVE_INTERVAL_HAS_HINTS into IR_LIVE_INTERVAL_HAS_HINT_REGS and
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IR_LIVE_INTERVAL_HAS_HINT_REFS
2023-05-18 10:48:31 +03:00
Dmitry Stogov
c9fa8dfebd
Fixed SSA deconstruction
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Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
2023-05-17 22:37:45 +03:00
Dmitry Stogov
af7117a3b7
Use cfg_map if available
2023-05-17 11:14:34 +03:00
Dmitry Stogov
d859591943
Inline fast path
2023-05-05 18:37:14 +03:00
Dmitry Stogov
c3fca224ff
Introduce IR_OP_FLAG_PINNED and IR_BB_HAS_PHI/PI/PARAM/VAR flags
2023-05-05 16:59:22 +03:00
Dmitry Stogov
1150c80ca2
Fixed support for OSR ENTRY
2023-05-05 12:59:33 +03:00
Dmitry Stogov
76f44fa126
Implemented path-exploration based live ranges construction
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The algorithm is based on "Computing Liveness Sets for SSA-Form Programs",
Florian Brandner, Benoit Boissinot, Alain Darte, Benoit Dupont de Dinechin,
Fabrice Rastello. TR Inria RR-7503, 2011
In comparison to the existing bitset based approach, the new algorithm
is more memory-space efficient and faster on big functions.
2023-05-05 02:01:53 +03:00
Dmitry Stogov
ac3a11e911
Improve ir_add_live_range(). Set ival->type when process definition.
2023-05-04 12:23:40 +03:00
Dmitry Stogov
d30f523c62
Avoid iteration over an empty bitset
2023-05-03 12:30:05 +03:00
Dmitry Stogov
1bbee7b9da
Get rid of ir_live_interval.top
2023-04-28 09:49:12 +03:00
Dmitry Stogov
0de0c1d0fa
Improve parallel copy algorithm to support move of single source into multiple destinations
2023-04-26 10:56:55 +03:00
Dmitry Stogov
1749168078
Add ir_insn_len() and ir_insn_inputs_to_len() private helpers
2023-04-21 13:40:55 +03:00
Dmitry Stogov
e01c43a967
Simplify access to nodes with variable inputs count
2023-04-21 12:40:17 +03:00
Dmitry Stogov
ac7f9a3a02
Improve ir_compute_live_ranges()
2023-04-14 01:47:47 +03:00
Dmitry Stogov
1115e7fb6e
cleanup
2023-04-13 21:45:38 +03:00
Dmitry Stogov
2a17b87219
LSRA optimization
2023-04-13 20:56:49 +03:00
Dmitry Stogov
e5c01495da
Use arena to allocate live_intervals and nested data structures
2023-04-13 13:47:16 +03:00
Dmitry Stogov
0b78a322f8
Cache deleted live ranges in ir_ctx.unused_ranges
2023-04-13 11:42:47 +03:00
Dmitry Stogov
7d395532d9
Simplify ir_assign_virtual_registers()
2023-04-13 03:01:08 +03:00
Dmitry Stogov
f85f5fd2a8
Remove data dependency between TAILCALL and UNREACHABLE
2023-04-13 02:41:28 +03:00
Dmitry Stogov
d71cbd47d5
Disable LICM across an OSR ENTRY if the value can't be restored at OSR ENTRY point
2023-04-07 16:36:27 +03:00
Dmitry Stogov
efa8a83153
Fix spilling code for arguments passed theought stack and change RA to
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prefer reusing the same register for splitted intervals
i# utils/
2023-04-06 00:16:49 +03:00
Dmitry Stogov
1e5e9e08ce
Re-implement instruction fusion and live-range construction
2023-04-05 19:20:43 +03:00
