ir/tests/x86/ra_015.irt
Dmitry Stogov 7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
2023-06-29 12:42:44 +03:00

25 lines
403 B
Plaintext

--TEST--
015: Register Allocation (SHL + SHL + reuse/vreg hint)
--TARGET--
x86
--ARGS--
-S
--CODE--
{
l_1 = START(l_4);
uint32_t x = PARAM(l_1, "x", 1);
uint32_t y = PARAM(l_1, "y", 2);
uint32_t ret = SHL(x, y);
uint32_t ret2 = SHL(y, ret);
l_4 = RETURN(l_1, ret2);
}
--EXPECT--
test:
movl 8(%esp), %eax
movl %eax, %ecx
movl 4(%esp), %edx
shll %cl, %edx
movl %edx, %ecx
shll %cl, %eax
retl