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abs_001.irt
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Better usage of the register hints
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2023-06-09 16:26:15 +03:00 |
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abs_002.irt
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abs_003.irt
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add_001.irt
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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add_002.irt
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add_003.irt
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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add_004.irt
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add_005.irt
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add_006.irt
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add_007.irt
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add_008.irt
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add_009.irt
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Extend test suite to support XFAIL section
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2022-11-22 10:43:29 +03:00 |
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add_010.irt
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add_011.irt
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add_012.irt
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add_ov_001.irt
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add_ov_002.irt
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add_ov_003.irt
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add_ov_004.irt
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alloca_001.irt
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alloca_002.irt
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bswap_001.irt
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cond_001.irt
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Implemented code generation for COND (not optimized)
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2023-10-13 20:50:23 +03:00 |
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cond_002.irt
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Implemented code generation for COND (not optimized)
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2023-10-13 20:50:23 +03:00 |
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cond_003.irt
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Implemented code generation for COND (not optimized)
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2023-10-13 20:50:23 +03:00 |
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cond_004.irt
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Implemented code generation for COND (not optimized)
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2023-10-13 20:50:23 +03:00 |
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conv_001.irt
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Extend test suite to support XFAIL section
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2022-11-22 10:43:29 +03:00 |
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conv_002.irt
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Extend test suite to support XFAIL section
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2022-11-22 10:43:29 +03:00 |
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conv_003.irt
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conv_004.irt
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Avoid MOVD/MOVQ disassemble mismatch with old/new capstone versions
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2023-09-19 16:30:09 +03:00 |
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conv_005.irt
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conv_006.irt
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Clear destination regeister before INT to FP conversion to avoid partial register stall
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2022-12-28 00:05:23 +03:00 |
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conv_007.irt
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conv_008.irt
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conv_009.irt
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conv_010.irt
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Avoid MOVD/MOVQ disassemble mismatch with old/new capstone versions
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2023-09-19 16:30:09 +03:00 |
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conv_011.irt
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div_001.irt
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div_002.irt
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div_003.irt
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div_004.irt
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div_005.irt
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div_006.irt
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eq_001.irt
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eq_002.irt
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eq_003.irt
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eq_004.irt
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eq_005.irt
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ge_001.irt
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ge_002.irt
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ge_003.irt
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ge_004.irt
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ge_005.irt
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gt_001.irt
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gt_002.irt
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gt_003.irt
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gt_004.irt
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gt_005.irt
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if_001.irt
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jcc_001.irt
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le_001.irt
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le_002.irt
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le_003.irt
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le_004.irt
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le_005.irt
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lt_001.irt
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lt_002.irt
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lt_003.irt
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lt_004.irt
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lt_005.irt
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min_001.irt
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min_002.irt
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min_003.irt
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min_004.irt
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min_005.irt
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Better usage of the register hints
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2023-06-09 16:26:15 +03:00 |
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min_006.irt
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Better usage of the register hints
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2023-06-09 16:26:15 +03:00 |
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min_007.irt
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Fix incorrect conditions
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2022-12-01 00:43:42 +03:00 |
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mod_001.irt
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mod_002.irt
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mod_003.irt
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mod_004.irt
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mod_005.irt
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mul_001.irt
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Use IMUL instead of MUL
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2022-12-16 12:57:40 +03:00 |
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mul_002.irt
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Use IMUL instead of MUL
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2022-12-16 12:57:40 +03:00 |
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mul_003.irt
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Use IMUL instead of MUL
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2022-12-16 12:57:40 +03:00 |
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mul_004.irt
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Use IMUL instead of MUL
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2022-12-16 12:57:40 +03:00 |
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mul_005.irt
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mul_006.irt
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mul_007.irt
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mul_ov_001.irt
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mul_ov_002.irt
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ne_001.irt
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ne_002.irt
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ne_003.irt
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ne_004.irt
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ne_005.irt
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neg_001.irt
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neg_002.irt
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neg_003.irt
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not_001.irt
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not_002.irt
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ra_001.irt
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Use IMUL instead of MUL
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2022-12-16 12:57:40 +03:00 |
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ra_002.irt
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Use IMUL instead of MUL
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2022-12-16 12:57:40 +03:00 |
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ra_003.irt
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Use IMUL instead of MUL
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2022-12-16 12:57:40 +03:00 |
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ra_004.irt
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Use IMUL instead of MUL
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2022-12-16 12:57:40 +03:00 |
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ra_005.irt
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ra_006.irt
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ra_007.irt
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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ra_008.irt
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ra_009.irt
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ra_010.irt
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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ra_011.irt
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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ra_012.irt
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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ra_013.irt
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ra_014.irt
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ra_015.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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setcc_001.irt
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shl_001.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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shl_002.irt
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shl_003.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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shl_004.irt
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sub_001.irt
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sub_002.irt
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sub_003.irt
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sub_004.irt
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sub_005.irt
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sub_006.irt
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sub_007.irt
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sub_008.irt
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sub_009.irt
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Extend test suite to support XFAIL section
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2022-11-22 10:43:29 +03:00 |
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sub_010.irt
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sub_011.irt
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sub_012.irt
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test_001.irt
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test_003.irt
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Fix fusion of IF(_, CMP(AND(_, _) 0))
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2023-03-28 19:03:06 +03:00 |
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test_004.irt
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Fix fusion of IF(_, CMP(AND(_, _) 0))
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2023-03-28 19:03:06 +03:00 |
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uge_001.irt
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uge_002.irt
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uge_003.irt
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ugt_001.irt
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ugt_002.irt
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ugt_003.irt
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ule_001.irt
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ule_002.irt
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ule_003.irt
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ult_001.irt
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ult_002.irt
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ult_003.irt
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