ir/tests/x86/shl_001.irt
Dmitry Stogov 7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
2023-06-29 12:42:44 +03:00

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--TEST--
001: shl function
--TARGET--
x86
--ARGS--
-S
--CODE--
{
l_1 = START(l_4);
int32_t x = PARAM(l_1, "x", 1);
int32_t y = PARAM(l_1, "y", 2);
int32_t ret = SHL(x, y);
l_4 = RETURN(l_1, ret);
}
--EXPECT--
test:
movl 8(%esp), %ecx
movl 4(%esp), %eax
shll %cl, %eax
retl