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args_001.irt
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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args_002.irt
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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call2.irt
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Fixed x86_64 calling convention for vararg functions
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2023-09-27 10:23:34 +03:00 |
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call3.irt
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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call_002.irt
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Improve x86 code generation for passing address of label to stack
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2023-03-29 15:48:41 +03:00 |
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call_alloca.irt
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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call_vaddr.irt
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Fixed tests
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2023-10-20 17:50:31 +03:00 |
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call-O0.irt
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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call.irt
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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combo_001.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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combo_002.irt
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Added type compatibility assertion and fixed mistakes in tests
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2023-05-22 20:48:07 +03:00 |
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combo_003.irt
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Added type compatibility assertion and fixed mistakes in tests
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2023-05-22 20:48:07 +03:00 |
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combo_004.irt
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Fixed mistakes in GCM algorithm
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2023-05-29 17:02:50 +03:00 |
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dce_001.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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dessa_001.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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dessa_002.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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dessa_003.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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fig-O0.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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fig.irt
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Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator"
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2023-06-28 22:00:50 +03:00 |
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ijmp_001.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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lea_001.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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loop_001.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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loop_002.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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memop_001.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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memop_002.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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memop_003.irt
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Improve load fusion, register allocateion and code selection for ADD
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2023-02-21 22:55:47 +03:00 |
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memop_004.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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memop_005.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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memop_006.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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memop_007.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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memop_008.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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params_001.irt
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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params_002.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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params_003.irt
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Fixed x86_64 calling convention for vararg functions
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2023-09-27 10:23:34 +03:00 |
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regset-fib2.irt
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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regset-fib.irt
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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regset-fibi.irt
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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regset-test.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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sccp_001.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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sccp_002.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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swap_001.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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swap_002.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
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switch_001.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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switch_002.irt
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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tailcall_001.irt
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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tailcall_002.irt
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Remove data dependency between TAILCALL and UNREACHABLE
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2023-04-13 02:41:28 +03:00 |
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test_mem.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test_var-O0.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test_var.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test-mavx.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test-O0.irt
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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test.irt
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More accurate spill loads optimization for instructions that reuse op1 register for result
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2023-06-29 12:42:44 +03:00 |
