ir/tests/debug/params_001.irt
Dmitry Stogov c9bb858e50 Fuse loads without register allocation when this makes sense.
Make oarameters passed through stack to reuse the same stack slot for spilling.
2022-05-19 10:53:08 +03:00

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--TEST--
001: Parameter Loading
--ARGS--
-S
--CODE--
{
l_1 = START(l_2);
int32_t p_1 = PARAM(l_1, "p_1", 1);
int32_t p_2 = PARAM(l_1, "p_2", 1);
int32_t p_3 = PARAM(l_1, "p_3", 1);
int32_t p_4 = PARAM(l_1, "p_4", 1);
int32_t p_5 = PARAM(l_1, "p_5", 1);
int32_t p_6 = PARAM(l_1, "p_6", 1);
int32_t p_7 = PARAM(l_1, "p_7", 1);
int32_t p_8 = PARAM(l_1, "p_8", 1);
int32_t p_9 = PARAM(l_1, "p_9", 1);
int32_t p_10 = PARAM(l_1, "p_10", 1);
int32_t r1 = ADD(p_1, p_2);
int32_t r2 = ADD(r1, p_3);
int32_t r3 = ADD(r2, p_4);
int32_t r4 = ADD(r3, p_5);
int32_t r5 = ADD(r4, p_6);
int32_t r6 = ADD(r5, p_7);
int32_t r7 = ADD(r6, p_8);
int32_t r8 = ADD(r7, p_9);
int32_t ret = SUB(r8, p_10);
l_2 = RETURN(l_1, ret);
}
--EXPECT--
test:
movl 8(%rsp), %eax
movl 0x10(%rsp), %r10d
movl 0x18(%rsp), %r11d
leal (%rsi, %rdi), %esi
leal (%rsi, %rdx), %edx
leal (%rdx, %rcx), %ecx
leal (%rcx, %r8), %ecx
leal (%rcx, %r9), %ecx
leal (%rcx, %rax), %eax
leal (%rax, %r10), %eax
leal (%rax, %r11), %eax
subl 0x20(%rsp), %eax
retq