Dmitry Stogov
|
688f876928
|
mplemented code-generation for bit counting instructions
|
2023-11-16 22:48:05 +03:00 |
|
Dmitry Stogov
|
92ef948caf
|
Implemented code-generation for CTPOP
|
2023-11-16 19:28:12 +03:00 |
|
Dmitry Stogov
|
d5596d815e
|
Stop reporting zero exit code when run JIT-ed code
|
2023-11-16 13:57:37 +03:00 |
|
Dmitry Stogov
|
1eaf5531e5
|
Fixed test
|
2023-11-08 10:20:55 +03:00 |
|
Dmitry Stogov
|
400fa2805d
|
An attempt to fix tests on Windows
|
2023-10-24 11:12:37 +03:00 |
|
Dmitry Stogov
|
6edb011548
|
Fixed code generation for unordered floating point comparison
- Fixed COND on AArch64
- Fixed SYM support on AArch64
|
2023-10-24 10:22:04 +03:00 |
|
Dmitry Stogov
|
d60d92516d
|
Fixed tests
|
2023-10-20 17:50:31 +03:00 |
|
Dmitry Stogov
|
49316643e7
|
Initial support for modules (incomplete)
|
2023-10-20 17:44:45 +03:00 |
|
Dmitry Stogov
|
9b1ce974cb
|
Improve loader interface (incomplete)
|
2023-10-20 01:09:46 +03:00 |
|
Dmitry Stogov
|
4f9724a7fb
|
Fix tests
|
2023-10-13 21:04:38 +03:00 |
|
Dmitry Stogov
|
66e9693019
|
Fix tests
|
2023-10-13 20:57:42 +03:00 |
|
Dmitry Stogov
|
613fca0327
|
Implemented code generation for COND (not optimized)
|
2023-10-13 20:50:23 +03:00 |
|
Dmitry Stogov
|
dd227dfa25
|
New tests
|
2023-10-12 15:01:27 +03:00 |
|
Dmitry Stogov
|
1970a16496
|
Fixed crash on dead PHI
|
2023-10-12 14:54:23 +03:00 |
|
Dmitry Stogov
|
211884cf29
|
Introduce API to load modules
|
2023-10-11 22:55:25 +03:00 |
|
Javier Eguiluz
|
2f4f8504d4
|
Fix some typos (#51)
|
2023-10-03 08:34:02 +03:00 |
|
Dmitry Stogov
|
9ea551a34f
|
LLVM support for fastcall and vararg
|
2023-09-29 11:30:53 +03:00 |
|
Dmitry Stogov
|
51a37f159b
|
Initial implementation of LLVM export
|
2023-09-28 20:44:45 +03:00 |
|
Dmitry Stogov
|
09829a9e69
|
Fixed x86_64 calling convention for vararg functions
%al is used as a hidden register to specify the number of passed vector registers
|
2023-09-27 10:23:34 +03:00 |
|
Dmitry Stogov
|
399a387713
|
Avoid MOVD/MOVQ disassemble mismatch with old/new capstone versions
|
2023-09-19 16:30:09 +03:00 |
|
Dmitry Stogov
|
7650500a7c
|
Remove -nan
|
2023-09-12 22:15:36 +03:00 |
|
Dmitry Stogov
|
834eb77e90
|
Fixed support for float, inf and nan constants.
|
2023-09-12 22:05:11 +03:00 |
|
Dmitry Stogov
|
0dbb794399
|
CI tests for MACOS build (#46)
|
2023-08-30 15:24:12 +03:00 |
|
Dmitry Stogov
|
7058c41411
|
More accurate spill loads optimization for instructions that reuse op1 register for result
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
|
2023-06-29 12:42:44 +03:00 |
|
Dmitry Stogov
|
2bfe1626ad
|
Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator"
|
2023-06-28 22:00:50 +03:00 |
|
Dmitry Stogov
|
141d46f5d8
|
Fixed tests
|
2023-06-27 11:34:13 +03:00 |
|
Dmitry Stogov
|
8a5a81c03e
|
Improve live interval splitting and eliminate more redundand spill loads
|
2023-06-27 11:29:26 +03:00 |
|
Dmitry Stogov
|
678a6af863
|
Eliminate duplicate spill loads at the same basic block
|
2023-06-22 14:41:01 +03:00 |
|
Dmitry Stogov
|
85beed7901
|
Fixed incorrect oredering of moves during de-SSA
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
|
2023-06-22 12:07:19 +03:00 |
|
Dmitry Stogov
|
35f94d570f
|
Revert "Eliminate duplicate spill loads at the same basic block"
This reverts commit 5d05d78462.
|
2023-06-22 01:58:26 +03:00 |
|
Dmitry Stogov
|
5d05d78462
|
Eliminate duplicate spill loads at the same basic block
|
2023-06-22 01:24:50 +03:00 |
|
Dmitry Stogov
|
ebaefd376a
|
Fix stack frame and assign all spill slots before code genearatin
|
2023-06-21 19:04:22 +03:00 |
|
Dmitry Stogov
|
ffac404552
|
Fix impossible load fusion
|
2023-06-20 12:14:52 +03:00 |
|
Dmitry Stogov
|
009e9c4a53
|
Split assign_regs() loop into two versions (with and without spilling).
|
2023-06-20 08:34:54 +03:00 |
|
Dmitry Stogov
|
cc87d1291f
|
Fixed tests
|
2023-06-09 16:29:38 +03:00 |
|
Dmitry Stogov
|
6a8830c1dc
|
Better usage of the register hints
|
2023-06-09 16:26:15 +03:00 |
|
Dmitry Stogov
|
0d3af66a2b
|
Fix test
|
2023-06-09 10:58:49 +03:00 |
|
Dmitry Stogov
|
b8be0b9dd9
|
Avoid loading of stack parameter to register if this is not necessary
|
2023-06-09 00:35:15 +03:00 |
|
Dmitry Stogov
|
186dc6b0a6
|
Fixed GH issue #33: IR program failed to compile with "-O0" "-S" options
|
2023-06-05 18:22:12 +03:00 |
|
Dmitry Stogov
|
b5bb5f869a
|
Fixed GH Issue #34 (Simple if-else IR program compile failure)
|
2023-06-05 14:21:03 +03:00 |
|
Dmitry Stogov
|
b560ddc8f6
|
Added test
|
2023-05-29 17:11:26 +03:00 |
|
Dmitry Stogov
|
c9d3804b6e
|
Fixed mistakes in GCM algorithm
|
2023-05-29 17:02:50 +03:00 |
|
Dmitry Stogov
|
4d2ef9401f
|
Fixed GH Issue #41 (ir_emit_c() dumping misses BB label)
|
2023-05-29 13:58:32 +03:00 |
|
Dmitry Stogov
|
75edc8fec5
|
Added type compatibility assertion and fixed mistakes in tests
|
2023-05-22 20:48:07 +03:00 |
|
Dmitry Stogov
|
3dcb083eb6
|
Fix Win64 tests
|
2023-05-17 22:49:26 +03:00 |
|
Dmitry Stogov
|
c9fa8dfebd
|
Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
|
2023-05-17 22:37:45 +03:00 |
|
Dmitry Stogov
|
53f4435f8e
|
Fixed test
|
2023-04-26 14:24:43 +03:00 |
|
Dmitry Stogov
|
60802d942f
|
Fix previous commit. We still need a temporary register for indirect calls.
|
2023-04-26 14:10:58 +03:00 |
|
Dmitry Stogov
|
9eb366698d
|
Avoid reservaton of temporary resiser for argument passing
We may use any scratch register that is not used for parameters
|
2023-04-26 12:16:05 +03:00 |
|
Dmitry Stogov
|
0de0c1d0fa
|
Improve parallel copy algorithm to support move of single source into multiple destinations
|
2023-04-26 10:56:55 +03:00 |
|