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Author	SHA1	Message	Date
Dmitry Stogov	74debb0bf4	Add "ir_load.c" to allow build without llk.php and initial multi-platform support	2022-10-26 19:52:14 +03:00
Dmitry Stogov	95e6cafe7c	cleanup	2022-10-26 16:06:16 +03:00
Dmitry Stogov	9b7835a05e	Use ir_emit_exitgroup() helper API instead of IR_EXITGROUP node	2022-10-26 15:46:59 +03:00
Dmitry Stogov	2dea40bfab	Add API to patch native code	2022-10-26 13:44:44 +03:00
Dmitry Stogov	edd7bc7101	Access ctx->rules[] trough inline function with assertion ... Fix incorrect accesses	2022-10-26 12:49:34 +03:00
Dmitry Stogov	b99d98979f	Limit CMP+GUARD fusing	2022-10-25 22:09:32 +03:00
Dmitry Stogov	006bee10c7	Add checks for constant references before checking the corresponding rule	2022-10-25 20:36:22 +03:00
Dmitry Stogov	4b114914dc	Prevent register clobbering	2022-10-25 12:24:05 +03:00
Dmitry Stogov	ba90e2825e	SNAPSHOT data shouldn't be in registers	2022-10-25 12:22:49 +03:00
Dmitry Stogov	265ebc1000	Fix two LSRA edge cases	2022-10-24 21:55:59 +03:00
Dmitry Stogov	9f472c1c91	Add support for deoptimization and binding to multiple slots	2022-10-21 17:16:25 +03:00
Dmitry Stogov	6667b7efae	Fix register allocation (one of operands MUST be in a register)	2022-10-21 12:02:31 +03:00
Dmitry Stogov	22cd9265d3	Check if the register is necessary at all	2022-10-18 22:02:09 +03:00
Dmitry Stogov	1dcfe127e1	Allow save/load "null" references	2022-10-18 15:52:25 +03:00
Dmitry Stogov	3d175e1576	Fix fuse load	2022-10-18 13:53:00 +03:00
Dmitry Stogov	ecb9719e8b	Fix "long" PHI handling	2022-10-12 14:01:56 +03:00
Dmitry Stogov	81c90972d6	Avoid useless spill stores	2022-10-12 12:09:52 +03:00
Dmitry Stogov	678da7fcc1	Use proper MOV instructions	2022-10-12 12:01:49 +03:00
Dmitry Stogov	6e0415a44d	Fix SCCP for PHIs	2022-10-12 12:01:28 +03:00
Dmitry Stogov	c74cac2556	Fix support for "long" PHIs	2022-10-12 11:59:49 +03:00
Dmitry Stogov	3ef58e5c2e	Take into account RLOADs for non fixed registers	2022-10-11 22:23:09 +03:00
Dmitry Stogov	f5c0151740	Remove hints to the same virtual register	2022-10-05 20:31:20 +03:00
Dmitry Stogov	e9402c8436	Add hint for "op1" if result reuses "op1" register. ... This improves register allocation if regiter for result was coalesced and allocated before the register for operand.	2022-10-05 17:58:37 +03:00
Dmitry Stogov	d2a0347b21	Merge basic blocks by removing connected END to BEGIN nodes	2022-10-05 16:29:49 +03:00
Dmitry Stogov	db8a80e8d5	Temporary remove "pxor". ... It should be added before all "cvt*" instructions	2022-09-29 20:05:00 +03:00
Dmitry Stogov	a98124a552	External __jit_debug_register_code() is necessary only on ARM	2022-09-29 17:10:32 +03:00
Dmitry Stogov	0da4b43de8	Fix second argument address	2022-09-29 14:17:54 +03:00
Dmitry Stogov	33bc4ce956	Fixed comparison with zero	2022-09-29 11:31:07 +03:00
Dmitry Stogov	a6e4e988d0	Fix ARM code generator	2022-09-29 02:10:44 +03:00
Dmitry Stogov	c3e6a71dda	Allow using external __jit_debug_register_code(). ... Fuinction defined in DSO may work improperly.	2022-09-29 01:28:30 +03:00
Dmitry Stogov	494c9225a9	Refactor trace related helpers	2022-09-29 01:25:42 +03:00
Dmitry Stogov	81f1108049	Add task	2022-09-28 21:58:38 +03:00
Dmitry Stogov	fdaa0cea54	Ignore dead TLS loads	2022-09-28 21:56:10 +03:00
Dmitry Stogov	a1361d77ba	Support for calling FASTCALL variable functions. ... Currutly this done through BITCAST hack. It may make sense to implement full support for function prototypes.	2022-09-28 20:48:35 +03:00
Dmitry Stogov	36b59306ee	Add task	2022-09-28 14:59:16 +03:00
Dmitry Stogov	66b62b7447	Fix use after reallocation	2022-09-28 14:31:46 +03:00
Dmitry Stogov	924f5949f2	Fixed SSE operands alignment and 32-bit support	2022-09-27 20:36:34 +03:00
Dmitry Stogov	408b8d2e4b	Fixed support for GUARD/GUARD_NOT	2022-09-27 16:52:15 +03:00
Dmitry Stogov	31220b1de9	Add code generators for missing GUARDs	2022-09-26 20:47:29 +03:00
Dmitry Stogov	da11454058	Fix incorrect code for IJMP	2022-09-26 14:45:12 +03:00
Dmitry Stogov	2b4a7d2cb3	Fix out of bounds array access	2022-09-23 12:36:11 +03:00
Dmitry Stogov	8f5768628a	Initial support for tracing JIT	2022-09-23 12:22:59 +03:00
Dmitry Stogov	05fd1f971d	Better LOAD fusion	2022-09-21 23:54:45 +03:00
Dmitry Stogov	12c183f391	Added support for GUARD_OVERFLOW	2022-09-20 17:38:27 +03:00
Dmitry Stogov	c186fb2c25	Fix constant address loading	2022-09-20 14:37:10 +03:00
Dmitry Stogov	45fff1fe5f	Implement binding IR node to VAR (assign spill slot)	2022-09-20 11:03:25 +03:00
Dmitry Stogov	ba748d5bd4	Simplify loop exit condition	2022-09-20 10:42:38 +03:00
Dmitry Stogov	23caf1e0d1	Fix incorrect starting operand number	2022-09-20 10:38:59 +03:00
Dmitry Stogov	63f21925b3	Avoid useless move	2022-09-20 00:26:56 +03:00
Dmitry Stogov	eacb9c1528	Avoid useless mov	2022-09-20 00:12:06 +03:00