Dmitry Stogov
|
4a39bda507
|
Fix double passing in 32-bit x86
|
2022-05-26 18:26:37 +03:00 |
|
Dmitry Stogov
|
4974c301bc
|
Fix code generation for preserved registers and dessa moves
|
2022-05-26 18:08:39 +03:00 |
|
Dmitry Stogov
|
f5bbdeea27
|
Fix buffer overflow
|
2022-05-26 17:19:43 +03:00 |
|
Dmitry Stogov
|
62d7fa7147
|
Fix string argument passing
|
2022-05-26 16:34:01 +03:00 |
|
Dmitry Stogov
|
0eef46493e
|
Improve code generation
|
2022-05-26 16:01:29 +03:00 |
|
Dmitry Stogov
|
8aac74dfb7
|
Improve code generation
|
2022-05-26 15:52:42 +03:00 |
|
Dmitry Stogov
|
2917dbbd59
|
Fix register clobbering
|
2022-05-26 15:26:04 +03:00 |
|
Dmitry Stogov
|
4862d69609
|
Improve code generation by load fusing
|
2022-05-26 14:43:19 +03:00 |
|
Dmitry Stogov
|
4598bd5b12
|
Better 32/64-bit assertions
|
2022-05-26 13:37:15 +03:00 |
|
Dmitry Stogov
|
e9fe55faa0
|
Fix param spill-slot assignment in 32-bit back-end
|
2022-05-26 13:09:20 +03:00 |
|
Dmitry Stogov
|
e28a3c801e
|
Fix retutn FP numbers for 32-bit x86 back-end
|
2022-05-26 11:58:51 +03:00 |
|
Dmitry Stogov
|
7e782a291a
|
Extend disassembler to support .rodata section and IP relative data labels
|
2022-05-26 01:17:02 +03:00 |
|
Dmitry Stogov
|
ead2b69fc6
|
x86_32 backend (incomplete)
|
2022-05-25 22:00:18 +03:00 |
|
Dmitry Stogov
|
19e93fd3f6
|
Allow multi-target test suite
|
2022-05-25 17:38:22 +03:00 |
|
Dmitry Stogov
|
235c1f2d65
|
Fix stack parameter loading for x86_32
|
2022-05-25 15:53:21 +03:00 |
|
Dmitry Stogov
|
341e3b8083
|
Initial support for x86_32 backend (incomplete)
|
2022-05-25 14:58:39 +03:00 |
|
Dmitry Stogov
|
4747a22474
|
Update tasks
|
2022-05-25 12:04:33 +03:00 |
|
Dmitry Stogov
|
ac65d71964
|
ws
|
2022-05-25 12:02:31 +03:00 |
|
Dmitry Stogov
|
9215162833
|
Ger rid of ir_ctx.bb_num and double neaning of ir_ctx.prev_insn_len
|
2022-05-25 11:58:35 +03:00 |
|
Dmitry Stogov
|
740cac8e2f
|
Move ir_ctx.unused_live_ranges to local variable
|
2022-05-25 10:57:21 +03:00 |
|
Dmitry Stogov
|
ab220de623
|
Fitsr and last instructions of BB and leading PARAM, PHI, PI, VAR instructions don't need to be scheduled.
|
2022-05-25 09:43:53 +03:00 |
|
Dmitry Stogov
|
463002107a
|
Rename "gcm_blocks" into "cfg_map"
|
2022-05-25 09:33:47 +03:00 |
|
Dmitry Stogov
|
87e9780a5b
|
Fixed handling of constant references
|
2022-05-25 09:30:26 +03:00 |
|
Dmitry Stogov
|
58b67fec18
|
Topological sort of nodes in each basic block
|
2022-05-24 18:04:38 +03:00 |
|
Dmitry Stogov
|
ddd5b739db
|
Update tasks
|
2022-05-24 12:59:57 +03:00 |
|
Dmitry Stogov
|
04667faf22
|
Reorder blocks according to branch probability
|
2022-05-24 12:47:39 +03:00 |
|
Dmitry Stogov
|
d3c1e4a02f
|
Reorder basic blocks to reduce number of jumps and improve code locality
|
2022-05-24 00:43:35 +03:00 |
|
Dmitry Stogov
|
596f03f263
|
Update tasks
|
2022-05-23 19:34:09 +03:00 |
|
Dmitry Stogov
|
fa36dbf9af
|
Update tasks
|
2022-05-20 13:09:41 +03:00 |
|
Dmitry Stogov
|
6f7f7b1268
|
Implement code generation for type conversion instructions
Register constraints might need to be tweeked.
|
2022-05-20 13:07:41 +03:00 |
|
Dmitry Stogov
|
c464b123cb
|
Add test for TRUNC
|
2022-05-20 09:09:52 +03:00 |
|
Dmitry Stogov
|
d250f77713
|
Improve type conversion nodes
|
2022-05-20 09:00:13 +03:00 |
|
Dmitry Stogov
|
c6b0e95d6b
|
Add type conversion nodes (no code generation yet)
|
2022-05-20 01:01:48 +03:00 |
|
Dmitry Stogov
|
41a76b39d8
|
update tasks
|
2022-05-19 22:12:20 +03:00 |
|
Dmitry Stogov
|
911219493d
|
Implement IJMP instruction (indirect jump or computed goto)
|
2022-05-19 18:56:48 +03:00 |
|
Dmitry Stogov
|
bae7df6a5f
|
Implement code generation for MIN and MAX instructions
|
2022-05-19 17:03:00 +03:00 |
|
Dmitry Stogov
|
8ccb7bc13a
|
Implement overflow checks
|
2022-05-19 15:49:47 +03:00 |
|
Dmitry Stogov
|
09cee45fd0
|
Fix compilation warnings
|
2022-05-19 14:40:57 +03:00 |
|
Dmitry Stogov
|
113b76c867
|
Add support for instructions that modify result directly in memory for LOAD/STORE
|
2022-05-19 14:04:29 +03:00 |
|
Dmitry Stogov
|
bf369d0eac
|
Swap operands for better load fusion
|
2022-05-19 13:17:50 +03:00 |
|
Dmitry Stogov
|
58063dd470
|
Update tasks
|
2022-05-19 11:02:39 +03:00 |
|
Dmitry Stogov
|
c9bb858e50
|
Fuse loads without register allocation when this makes sense.
Make oarameters passed through stack to reuse the same stack slot for spilling.
|
2022-05-19 10:53:08 +03:00 |
|
Dmitry Stogov
|
1af065058b
|
Use better name
|
2022-05-19 09:15:45 +03:00 |
|
Dmitry Stogov
|
b77f722cb9
|
cleanup
|
2022-05-19 09:11:51 +03:00 |
|
Dmitry Stogov
|
88ab04a3c2
|
New tests
|
2022-05-18 23:53:16 +03:00 |
|
Dmitry Stogov
|
177e556754
|
Fix spill slot comparison
|
2022-05-18 23:44:59 +03:00 |
|
Dmitry Stogov
|
cdd39f22b0
|
Merge spills for VSTORE with -O0
|
2022-05-18 23:12:20 +03:00 |
|
Dmitry Stogov
|
c5a24ff734
|
Add support for instructions that modify result directly in memory
|
2022-05-18 21:49:08 +03:00 |
|
Dmitry Stogov
|
e9e214d7d9
|
Remove special support for "_spill_" variable
|
2022-05-18 17:32:32 +03:00 |
|
Dmitry Stogov
|
2507dde1ad
|
Fix stack alignment
|
2022-05-18 14:42:03 +03:00 |
|