Dmitry Stogov
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87f2fc7f69
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Fixed typo
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2023-05-29 15:52:17 +03:00 |
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Dmitry Stogov
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20b9a7513c
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Fixed missing label
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2023-05-26 09:08:57 +03:00 |
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Dmitry Stogov
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2a80257535
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Support for more C escape sequences
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2023-05-22 19:51:19 +03:00 |
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Dmitry Stogov
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d3640495a2
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Ceanup ir_compute_live_ranges() implementation
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2023-05-19 12:34:54 +03:00 |
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Dmitry Stogov
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5c2023fd7f
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Avoid live range constrction for VARs
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2023-05-18 21:00:57 +03:00 |
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Dmitry Stogov
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477dbf7d76
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Avoid live range constrction for RLOAD with fixed registers
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2023-05-18 13:37:12 +03:00 |
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Dmitry Stogov
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c9fa8dfebd
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Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
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2023-05-17 22:37:45 +03:00 |
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Dmitry Stogov
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1bbee7b9da
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Get rid of ir_live_interval.top
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2023-04-28 09:49:12 +03:00 |
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Dmitry Stogov
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60802d942f
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Fix previous commit. We still need a temporary register for indirect calls.
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2023-04-26 14:10:58 +03:00 |
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Dmitry Stogov
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9eb366698d
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Avoid reservaton of temporary resiser for argument passing
We may use any scratch register that is not used for parameters
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2023-04-26 12:16:05 +03:00 |
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Dmitry Stogov
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0de0c1d0fa
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Improve parallel copy algorithm to support move of single source into multiple destinations
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2023-04-26 10:56:55 +03:00 |
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Dmitry Stogov
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1749168078
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Add ir_insn_len() and ir_insn_inputs_to_len() private helpers
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2023-04-21 13:40:55 +03:00 |
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Dmitry Stogov
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e01c43a967
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Simplify access to nodes with variable inputs count
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2023-04-21 12:40:17 +03:00 |
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Dmitry Stogov
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e5c01495da
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Use arena to allocate live_intervals and nested data structures
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2023-04-13 13:47:16 +03:00 |
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Dmitry Stogov
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04795b9f04
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Fix compilation warnings
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2023-04-12 10:48:30 +03:00 |
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Dmitry Stogov
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1e5e9e08ce
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Re-implement instruction fusion and live-range construction
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2023-04-05 19:20:43 +03:00 |
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Dmitry Stogov
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1058cde808
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Cleanup instruction selector
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2023-03-29 01:21:54 +03:00 |
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Dmitry Stogov
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ba0fa44447
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Add "const" modifiers
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2023-03-28 13:18:12 +03:00 |
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Dmitry Stogov
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72a5649236
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Reorder conditions and avoid reloading
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2023-03-23 23:44:59 +03:00 |
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Dmitry Stogov
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7e687262f7
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Remove always true conditions
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2023-03-23 22:16:05 +03:00 |
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Dmitry Stogov
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87dbdcea0d
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Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point
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2023-03-21 13:45:37 +03:00 |
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Dmitry Stogov
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f5b7065b10
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Refactor the ENTRY nodes
Now all ENTRY nodes have a "fake" input control edge.
Through this edge all of them are dominated by START node.
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2023-03-17 09:02:37 +03:00 |
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Dmitry Stogov
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5052a6ca97
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Fix stack alignment and allow non-saved permanent registers in the "fixed" frames
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2023-03-07 21:38:27 +03:00 |
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Dmitry Stogov
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9b34731d16
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Fix most MSVC compilation warnings
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2023-02-28 02:11:09 +03:00 |
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Dmitry Stogov
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637fe28e90
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Add comments
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2023-02-21 15:41:41 +03:00 |
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Dmitry Stogov
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9f81982d86
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Fix 'mov' to/from 'sp' register
sp is shared with zero register and 'mov' for sp/xzr is encoded differently
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2023-02-21 11:42:05 +03:00 |
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Dmitry Stogov
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c71076d3f0
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Allow reservation stack for passing arguments
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2023-02-17 15:52:26 +03:00 |
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Dmitry Stogov
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fd653528e9
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JMP optimization. Lift constant IJMP targets into jmp_table(s).
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2023-02-16 22:41:55 +03:00 |
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Dmitry Stogov
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038b1e43cd
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We can't preallocate stack for fastcall function calls
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2023-01-31 16:13:15 +03:00 |
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Dmitry Stogov
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677c6cb2cb
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Move declaration of some register alloation related macros to public API
Use RLOAD.op3 as a flag to avoid spill store
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2023-01-30 16:33:57 +03:00 |
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Dmitry Stogov
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bbfcb3e8c8
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Fix register allocation for MUL_OV in a different way
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2023-01-26 13:20:08 +03:00 |
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Dmitry Stogov
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4fb50d85aa
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Add assertion when allocated preserved register is not saved in "fixed" frame prologue
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2023-01-26 12:49:23 +03:00 |
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Dmitry Stogov
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761c50488e
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Fix incorrect code generation
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2023-01-26 11:50:10 +03:00 |
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Dmitry Stogov
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4a67399005
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Fix integer MUL overflow checks
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2023-01-26 10:08:40 +03:00 |
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Dmitry Stogov
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771da56d07
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Fix incorrect tests for empty basic blocks
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2023-01-24 11:48:21 +03:00 |
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Dmitry Stogov
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a5c0514b13
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Use better conditions
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2023-01-23 16:05:06 +03:00 |
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Dmitry Stogov
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32ad3d1052
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Use inline functions to avoid false positive address sanitaizer warnings
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2023-01-20 15:35:02 +03:00 |
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Dmitry Stogov
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3ac58893f2
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Fix address sanitizer warnings
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2023-01-20 11:30:22 +03:00 |
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Dmitry Stogov
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208e0040ae
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Prefer 'ADD [addr], %r1' over 'mov [addr], %r1; lea [%r1, %r2], %r3'
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2022-12-28 22:24:42 +03:00 |
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Dmitry Stogov
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cc8f3fe987
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Fix register allocation for intervals started by RLOAD of non-fixed register.
These intervals may be split and spilled.
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2022-12-27 22:34:52 +03:00 |
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Dmitry Stogov
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d528d29872
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Fix memory leaks in case of dynasm errors and JIT buffer overflow
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2022-12-26 20:58:54 +03:00 |
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Dmitry Stogov
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67da9e93ea
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Fix register clobbering during argument passing and spill load
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2022-12-26 20:25:11 +03:00 |
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Dmitry Stogov
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d26b162ffa
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Fix register clobbering during argument passing
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2022-12-26 18:27:53 +03:00 |
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Dmitry Stogov
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9f0bf4849f
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Fix build
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2022-12-26 14:44:57 +03:00 |
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Dmitry Stogov
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1df594fea5
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Fix memory leak
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2022-12-26 14:17:48 +03:00 |
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Dmitry Stogov
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4d7386d342
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Fix support for spill loads
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2022-12-15 23:27:30 +03:00 |
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Dmitry Stogov
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52842a094a
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Require temporary register for passing argument through stack
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2022-12-12 18:14:31 +03:00 |
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Dmitry Stogov
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6790ebf3b5
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Implement AFREE instruction to revert ALLOCA
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2022-12-07 13:09:00 +03:00 |
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Dmitry Stogov
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efbc51baaa
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Fixed codegeneration for TRUNC on aarch64
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2022-12-07 11:56:53 +03:00 |
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Dmitry Stogov
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374df90797
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Fix missing sill store
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2022-12-07 00:02:02 +03:00 |
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