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cc73788981
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250 Commits

Author SHA1 Message Date
Dmitry Stogov
cc73788981 Fix compilation warnings 2022-11-08 18:17:29 +03:00
Dmitry Stogov
cc56f12f13 Add LICENSE and copyright notices 2022-11-08 11:32:46 +03:00
Dmitry Stogov
d619efa0ad Add support for ENDBR 2022-10-27 12:58:04 +03:00
Dmitry Stogov
3af9e1a062 Move some common code into ir_emit.c 2022-10-26 22:52:19 +03:00
Dmitry Stogov
1b84570aa3 Intoduce ir_emit.c that shuould keep common part for different targets 2022-10-26 22:06:07 +03:00
Dmitry Stogov
9b7835a05e Use ir_emit_exitgroup() helper API instead of IR_EXITGROUP node 2022-10-26 15:46:59 +03:00
Dmitry Stogov
2dea40bfab Add API to patch native code 2022-10-26 13:44:44 +03:00
Dmitry Stogov
edd7bc7101 Access ctx->rules[] trough inline function with assertion 
Fix incorrect accesses
 2022-10-26 12:49:34 +03:00
Dmitry Stogov
b99d98979f Limit CMP+GUARD fusing 2022-10-25 22:09:32 +03:00
Dmitry Stogov
006bee10c7 Add checks for constant references before checking the corresponding rule 2022-10-25 20:36:22 +03:00
Dmitry Stogov
ba90e2825e SNAPSHOT data shouldn't be in registers 2022-10-25 12:22:49 +03:00
Dmitry Stogov
9f472c1c91 Add support for deoptimization and binding to multiple slots 2022-10-21 17:16:25 +03:00
Dmitry Stogov
6667b7efae Fix register allocation (one of operands MUST be in a register) 2022-10-21 12:02:31 +03:00
Dmitry Stogov
3d175e1576 Fix fuse load 2022-10-18 13:53:00 +03:00
Dmitry Stogov
81c90972d6 Avoid useless spill stores 2022-10-12 12:09:52 +03:00
Dmitry Stogov
678da7fcc1 Use proper MOV instructions 2022-10-12 12:01:49 +03:00
Dmitry Stogov
db8a80e8d5 Temporary remove "pxor". 
It should be added before all "cvt*" instructions
 2022-09-29 20:05:00 +03:00
Dmitry Stogov
0da4b43de8 Fix second argument address 2022-09-29 14:17:54 +03:00
Dmitry Stogov
33bc4ce956 Fixed comparison with zero 2022-09-29 11:31:07 +03:00
Dmitry Stogov
494c9225a9 Refactor trace related helpers 2022-09-29 01:25:42 +03:00
Dmitry Stogov
fdaa0cea54 Ignore dead TLS loads 2022-09-28 21:56:10 +03:00
Dmitry Stogov
a1361d77ba Support for calling FASTCALL variable functions. 
Currutly this done through BITCAST hack.
It may make sense to implement full support for function prototypes.
 2022-09-28 20:48:35 +03:00
Dmitry Stogov
924f5949f2 Fixed SSE operands alignment and 32-bit support 2022-09-27 20:36:34 +03:00
Dmitry Stogov
408b8d2e4b Fixed support for GUARD/GUARD_NOT 2022-09-27 16:52:15 +03:00
Dmitry Stogov
31220b1de9 Add code generators for missing GUARDs 2022-09-26 20:47:29 +03:00
Dmitry Stogov
da11454058 Fix incorrect code for IJMP 2022-09-26 14:45:12 +03:00
Dmitry Stogov
2b4a7d2cb3 Fix out of bounds array access 2022-09-23 12:36:11 +03:00
Dmitry Stogov
8f5768628a Initial support for tracing JIT 2022-09-23 12:22:59 +03:00
Dmitry Stogov
05fd1f971d Better LOAD fusion 2022-09-21 23:54:45 +03:00
Dmitry Stogov
12c183f391 Added support for GUARD_OVERFLOW 2022-09-20 17:38:27 +03:00
Dmitry Stogov
c186fb2c25 Fix constant address loading 2022-09-20 14:37:10 +03:00
Dmitry Stogov
63f21925b3 Avoid useless move 2022-09-20 00:26:56 +03:00
Dmitry Stogov
eacb9c1528 Avoid useless mov 2022-09-20 00:12:06 +03:00
Dmitry Stogov
b519f80da5 More accurte fusion of address calculation 2022-09-16 12:05:36 +03:00
Dmitry Stogov
86bec14bc2 Fixed fuse loading in BITCAST 2022-09-16 10:19:31 +03:00
Dmitry Stogov
4a8ebd5be5 Fuse function address load into CALL/TAILCALL without arguments 2022-09-16 09:54:49 +03:00
Dmitry Stogov
57a9731179 Fix spill load code 2022-09-15 23:24:28 +03:00
Dmitry Stogov
b549d98aba The second operand for MEM_BINOP_INT must be in a register 2022-09-15 20:29:30 +03:00
Dmitry Stogov
367e47ac30 Support for preallocated stack (ZEND_VM_HYBRID_JIT_RED_ZONE_SIZE in PHP VM) 2022-09-15 15:39:15 +03:00
Dmitry Stogov
ad59556d85 Add support for binding IR nodes to "external" spill slots (e.g. PHP VM stack slots) 2022-09-15 15:26:43 +03:00
Dmitry Stogov
5f4b42155f ctx->rules[] is valid only for non CONST IR reference 2022-09-14 15:54:24 +03:00
Dmitry Stogov
05bc456c6a Move base regester selection code into ir_ref_spill_slot() 2022-09-07 23:47:30 +03:00
Dmitry Stogov
2677299bbd Fix invalid type 2022-09-07 22:21:12 +03:00
Dmitry Stogov
b68c4db601 Don't fuse LOAD into instruction in diffrent basic block 2022-09-06 14:01:35 +03:00
Dmitry Stogov
8600801c1f Eliminate identical comparisons 2022-09-05 14:41:38 +03:00
Dmitry Stogov
fb0d5fd87c Improve GUARD instructions support 2022-09-02 13:54:31 +03:00
Dmitry Stogov
c865599451 Fix code generation 2022-09-02 13:12:58 +03:00
Dmitry Stogov
5034f8dedb Allow genearion of TEST MEM, IMM 2022-09-01 22:25:29 +03:00
Dmitry Stogov
9b558e544f Allow fusion of single address calculation instruction into several load/store instructions 
Previously, if calculated address were used in few places we kept it in a register (without
fusion).
 2022-09-01 20:40:29 +03:00
Dmitry Stogov
756a1afc82 Better register allocation support for address and load fusion 2022-09-01 19:19:01 +03:00