Dmitry Stogov
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d60d92516d
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Fixed tests
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2023-10-20 17:50:31 +03:00 |
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Dmitry Stogov
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49316643e7
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Initial support for modules (incomplete)
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2023-10-20 17:44:45 +03:00 |
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Dmitry Stogov
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9b1ce974cb
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Improve loader interface (incomplete)
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2023-10-20 01:09:46 +03:00 |
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Dmitry Stogov
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4f9724a7fb
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Fix tests
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2023-10-13 21:04:38 +03:00 |
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Dmitry Stogov
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66e9693019
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Fix tests
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2023-10-13 20:57:42 +03:00 |
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Dmitry Stogov
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613fca0327
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Implemented code generation for COND (not optimized)
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2023-10-13 20:50:23 +03:00 |
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Dmitry Stogov
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dd227dfa25
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New tests
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2023-10-12 15:01:27 +03:00 |
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Dmitry Stogov
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1970a16496
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Fixed crash on dead PHI
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2023-10-12 14:54:23 +03:00 |
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Dmitry Stogov
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211884cf29
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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Javier Eguiluz
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2f4f8504d4
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Fix some typos (#51)
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2023-10-03 08:34:02 +03:00 |
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Dmitry Stogov
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9ea551a34f
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LLVM support for fastcall and vararg
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2023-09-29 11:30:53 +03:00 |
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Dmitry Stogov
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51a37f159b
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Initial implementation of LLVM export
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2023-09-28 20:44:45 +03:00 |
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Dmitry Stogov
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09829a9e69
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Fixed x86_64 calling convention for vararg functions
%al is used as a hidden register to specify the number of passed vector registers
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2023-09-27 10:23:34 +03:00 |
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Dmitry Stogov
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399a387713
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Avoid MOVD/MOVQ disassemble mismatch with old/new capstone versions
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2023-09-19 16:30:09 +03:00 |
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Dmitry Stogov
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7650500a7c
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Remove -nan
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2023-09-12 22:15:36 +03:00 |
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Dmitry Stogov
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834eb77e90
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Fixed support for float, inf and nan constants.
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2023-09-12 22:05:11 +03:00 |
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Dmitry Stogov
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0dbb794399
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CI tests for MACOS build (#46)
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2023-08-30 15:24:12 +03:00 |
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Dmitry Stogov
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7058c41411
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More accurate spill loads optimization for instructions that reuse op1 register for result
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
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2023-06-29 12:42:44 +03:00 |
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Dmitry Stogov
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2bfe1626ad
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Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator"
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2023-06-28 22:00:50 +03:00 |
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Dmitry Stogov
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141d46f5d8
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Fixed tests
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2023-06-27 11:34:13 +03:00 |
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Dmitry Stogov
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8a5a81c03e
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Improve live interval splitting and eliminate more redundand spill loads
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2023-06-27 11:29:26 +03:00 |
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Dmitry Stogov
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678a6af863
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 14:41:01 +03:00 |
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Dmitry Stogov
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85beed7901
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Fixed incorrect oredering of moves during de-SSA
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
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2023-06-22 12:07:19 +03:00 |
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Dmitry Stogov
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35f94d570f
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Revert "Eliminate duplicate spill loads at the same basic block"
This reverts commit 5d05d78462.
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2023-06-22 01:58:26 +03:00 |
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Dmitry Stogov
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5d05d78462
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 01:24:50 +03:00 |
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Dmitry Stogov
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ebaefd376a
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Fix stack frame and assign all spill slots before code genearatin
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2023-06-21 19:04:22 +03:00 |
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Dmitry Stogov
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ffac404552
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Fix impossible load fusion
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2023-06-20 12:14:52 +03:00 |
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Dmitry Stogov
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009e9c4a53
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Split assign_regs() loop into two versions (with and without spilling).
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2023-06-20 08:34:54 +03:00 |
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Dmitry Stogov
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cc87d1291f
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Fixed tests
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2023-06-09 16:29:38 +03:00 |
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Dmitry Stogov
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6a8830c1dc
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Better usage of the register hints
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2023-06-09 16:26:15 +03:00 |
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Dmitry Stogov
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0d3af66a2b
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Fix test
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2023-06-09 10:58:49 +03:00 |
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Dmitry Stogov
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b8be0b9dd9
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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Dmitry Stogov
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186dc6b0a6
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Fixed GH issue #33: IR program failed to compile with "-O0" "-S" options
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2023-06-05 18:22:12 +03:00 |
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Dmitry Stogov
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b5bb5f869a
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Fixed GH Issue #34 (Simple if-else IR program compile failure)
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2023-06-05 14:21:03 +03:00 |
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Dmitry Stogov
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b560ddc8f6
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Added test
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2023-05-29 17:11:26 +03:00 |
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Dmitry Stogov
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c9d3804b6e
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Fixed mistakes in GCM algorithm
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2023-05-29 17:02:50 +03:00 |
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Dmitry Stogov
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4d2ef9401f
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Fixed GH Issue #41 (ir_emit_c() dumping misses BB label)
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2023-05-29 13:58:32 +03:00 |
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Dmitry Stogov
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75edc8fec5
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Added type compatibility assertion and fixed mistakes in tests
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2023-05-22 20:48:07 +03:00 |
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Dmitry Stogov
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3dcb083eb6
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Fix Win64 tests
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2023-05-17 22:49:26 +03:00 |
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Dmitry Stogov
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c9fa8dfebd
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Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
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2023-05-17 22:37:45 +03:00 |
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Dmitry Stogov
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53f4435f8e
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Fixed test
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2023-04-26 14:24:43 +03:00 |
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Dmitry Stogov
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60802d942f
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Fix previous commit. We still need a temporary register for indirect calls.
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2023-04-26 14:10:58 +03:00 |
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Dmitry Stogov
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9eb366698d
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Avoid reservaton of temporary resiser for argument passing
We may use any scratch register that is not used for parameters
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2023-04-26 12:16:05 +03:00 |
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Dmitry Stogov
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0de0c1d0fa
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Improve parallel copy algorithm to support move of single source into multiple destinations
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2023-04-26 10:56:55 +03:00 |
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Dmitry Stogov
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1f7a2bd243
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Remove useless "AVX" tests for AArch64
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2023-04-18 10:14:59 +03:00 |
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Dmitry Stogov
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f85f5fd2a8
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Remove data dependency between TAILCALL and UNREACHABLE
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2023-04-13 02:41:28 +03:00 |
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Dmitry Stogov
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efa8a83153
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Fix spilling code for arguments passed theought stack and change RA to
prefer reusing the same register for splitted intervals
i# utils/
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2023-04-06 00:16:49 +03:00 |
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Dmitry Stogov
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1e5e9e08ce
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Re-implement instruction fusion and live-range construction
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2023-04-05 19:20:43 +03:00 |
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Dmitry Stogov
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ee827ee983
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Don't create two DEF UsePos
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2023-03-29 17:22:49 +03:00 |
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Dmitry Stogov
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d79bd88f6f
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Improve x86 code generation for passing address of label to stack
- leal .L1, %eax
- movl %eax, (%esp)
+ movl $.L1, (%esp)
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2023-03-29 15:48:41 +03:00 |
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