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780 Commits

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Author SHA1 Message Date
Dmitry Stogov
761c50488e Fix incorrect code generation 2023-01-26 11:50:10 +03:00
Dmitry Stogov
4a67399005 Fix integer MUL overflow checks 2023-01-26 10:08:40 +03:00
Dmitry Stogov
0eff9e0516 Registers %r4b - %r7b are not available in 32-bit mode 2023-01-24 15:31:31 +03:00
Dmitry Stogov
01c4b95c18 Fix test for empty ENTRY block 2023-01-24 11:59:41 +03:00
Dmitry Stogov
771da56d07 Fix incorrect tests for empty basic blocks 2023-01-24 11:48:21 +03:00
Dmitry Stogov
a5c0514b13 Use better conditions 2023-01-23 16:05:06 +03:00
Dmitry Stogov
169033c291 RETURN may be followed by ENTRY 2023-01-23 16:04:11 +03:00
Dmitry Stogov
afc948def6 Fix 32-bit negation 2023-01-20 16:00:23 +03:00
Dmitry Stogov
32ad3d1052 Use inline functions to avoid false positive address sanitaizer warnings 2023-01-20 15:35:02 +03:00
Dmitry Stogov
3ac58893f2 Fix address sanitizer warnings 2023-01-20 11:30:22 +03:00
Dmitry Stogov
8c715480e3 Fix disassembler. Allow ENTRY references in jump tables. 2023-01-20 09:13:15 +03:00
Dmitry Stogov
5103c18269 Fix load fusion in combination with depended register spill load 2023-01-19 13:39:29 +03:00
Dmitry Stogov
a85f59a62d Fix MERGE to BEGIN conversion in SCCP 2023-01-19 10:08:48 +03:00
Dmitry Stogov
4bc47db08d Fix use_list update 2023-01-18 17:19:37 +03:00
Dmitry Stogov
29da69cf25 Fix CASE_VAL scheduling (mark op2 as used constant). 2023-01-18 09:38:18 +03:00
Dmitry Stogov
211677e2c2 Add check for SWITCH targets 2023-01-18 09:37:30 +03:00
Dmitry Stogov
397ed1696b Split at "max_pos" if "min_bb" is in a deeper loop than "max_bb" 2022-12-29 01:39:24 +03:00
Dmitry Stogov
208e0040ae Prefer 'ADD [addr], %r1' over 'mov [addr], %r1; lea [%r1, %r2], %r3' 2022-12-28 22:24:42 +03:00
Dmitry Stogov
e710f30170 Constant folding for MUL_OV 2022-12-28 09:10:39 +03:00
Dmitry Stogov
e067ff66f3 Allow fuse load of constant address 2022-12-28 09:10:16 +03:00
Dmitry Stogov
b043955723 First opernad of IMUL3 can not be constant 2022-12-28 09:09:19 +03:00
Dmitry Stogov
54597bc862 Clear destination regeister before INT to FP conversion to avoid partial register stall 2022-12-28 00:05:23 +03:00
Dmitry Stogov
cc8f3fe987 Fix register allocation for intervals started by RLOAD of non-fixed register. 
These intervals may be split and spilled.
 2022-12-27 22:34:52 +03:00
Dmitry Stogov
d528d29872 Fix memory leaks in case of dynasm errors and JIT buffer overflow 2022-12-26 20:58:54 +03:00
Dmitry Stogov
67da9e93ea Fix register clobbering during argument passing and spill load 2022-12-26 20:25:11 +03:00
Dmitry Stogov
d26b162ffa Fix register clobbering during argument passing 2022-12-26 18:27:53 +03:00
Dmitry Stogov
9f0bf4849f Fix build 2022-12-26 14:44:57 +03:00
Dmitry Stogov
1df594fea5 Fix memory leak 2022-12-26 14:17:48 +03:00
Dmitry Stogov
844653cfd1 Fix IR reconstruction during SCCP 2022-12-23 14:34:51 +03:00
Dmitry Stogov
862e25d96c Try allocationg another blocked register in case of unresolvable conflicts 2022-12-22 22:09:04 +03:00
Dmitry Stogov
cfa8dac9d9 Fix load fusion 2022-12-21 23:32:16 +03:00
Dmitry Stogov
1bff08bc10 Update use_lists when modify an instruction 2022-12-21 23:31:11 +03:00
Dmitry Stogov
53ead9d2e7 Generate better code for GUARD(_, AND(_, _), _) 2022-12-16 15:07:18 +03:00
Dmitry Stogov
e884e045de Avoid zero extension to the same register 2022-12-16 13:38:58 +03:00
Dmitry Stogov
95729f76bf Use IMUL instead of MUL 2022-12-16 12:57:40 +03:00
Dmitry Stogov
9e54343a62 Fix iteration through loop pre-headers 2022-12-15 23:28:09 +03:00
Dmitry Stogov
4d7386d342 Fix support for spill loads 2022-12-15 23:27:30 +03:00
Dmitry Stogov
1d01ce3a39 Add constant folding rulues for BITCAST 2022-12-15 23:26:45 +03:00
Dmitry Stogov
7773792716 Add constant folding rulues for ADDR 2022-12-15 22:03:25 +03:00
Dmitry Stogov
837c59156f Fix support for load fusion of constant address 2022-12-14 13:22:38 +03:00
Dmitry Stogov
47771c73bc Fix inaccurate address fusion 2022-12-13 17:40:08 +03:00
Dmitry Stogov
52842a094a Require temporary register for passing argument through stack 2022-12-12 18:14:31 +03:00
Dmitry Stogov
bfbae48e6f Fix load fusion with spilling 2022-12-09 15:08:43 +03:00
Dmitry Stogov
5959f5375b Fix missed register allocation for the rest of splitted inactive interval 2022-12-09 15:07:36 +03:00
Dmitry Stogov
6790ebf3b5 Implement AFREE instruction to revert ALLOCA 2022-12-07 13:09:00 +03:00
Dmitry Stogov
efbc51baaa Fixed codegeneration for TRUNC on aarch64 2022-12-07 11:56:53 +03:00
Dmitry Stogov
374df90797 Fix missing sill store 2022-12-07 00:02:02 +03:00
Dmitry Stogov
83d3480391 Fix incorrect spill load inside a fuse load 2022-12-06 23:37:10 +03:00
Dmitry Stogov
0f9d525157 Fix suport for load fusion with constant address 2022-12-05 20:06:42 +03:00
Dmitry Stogov
9dda4e7553 Add constant folding rulues for ADDR 2022-12-05 16:44:10 +03:00