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eb771b1fef
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315 Commits

Author SHA1 Message Date
Dmitry Stogov
eb771b1fef Fix incorrect shift operand 2023-02-28 02:22:09 +03:00
Dmitry Stogov
9b34731d16 Fix most MSVC compilation warnings 2023-02-28 02:11:09 +03:00
Dmitry Stogov
00d5e471ad Improve load fusion, register allocateion and code selection for ADD 2023-02-21 22:55:47 +03:00
Dmitry Stogov
637fe28e90 Add comments 2023-02-21 15:41:41 +03:00
Arnaud Le Blanc
e95cdd0722 Fix temporary register allocation for IR_STORE_INT 
ir_get_target_constraints() mistakenly tests the instruction type and value
instead of the operands'.
 2023-02-18 13:18:49 +01:00
Dmitry Stogov
2f2fed89bb Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32") 2023-02-17 18:11:13 +03:00
Dmitry Stogov
c71076d3f0 Allow reservation stack for passing arguments 2023-02-17 15:52:26 +03:00
Dmitry Stogov
fd653528e9 JMP optimization. Lift constant IJMP targets into jmp_table(s). 2023-02-16 22:41:55 +03:00
Dmitry Stogov
ec8489bf6f Fix spill load 2023-02-16 01:46:16 +03:00
Dmitry Stogov
c7e2cca534 Add hint to reuse register in ZEXT/SEXT 2023-02-15 18:33:02 +03:00
Dmitry Stogov
1d7ab16c2a Allow load fuson for CALL and TAILCALL with arguments 2023-02-14 14:51:12 +03:00
Dmitry Stogov
e19ecd94c3 Eliminate unnecessary "test" or comparison instruction for IF(CMP_OP(BIN_OP(_, _), 0)) 
TODO: this should be ported to ARM
 2023-02-14 11:25:16 +03:00
Dmitry Stogov
6a4187eacc Fixed CLANG build 2023-02-07 23:11:16 +03:00
Dmitry Stogov
d7ed2fdfad We can't relay on block order because they are re-scheduled later 2023-02-07 03:30:44 +03:00
Dmitry Stogov
2e31446e37 Better 'jp' elimination for IR_CMP_AND_BRANCH_FP 2023-02-07 01:57:07 +03:00
Dmitry Stogov
6521c0b7e4 Better 'jp' elimination for GUARDs 2023-02-07 01:06:30 +03:00
Dmitry Stogov
1773bb81aa Make a decision about load fusion and operand swapping together 2023-02-05 14:48:14 +03:00
Dmitry Stogov
cfc959d8ca Better load fusion 2023-02-03 12:50:00 +03:00
Dmitry Stogov
dc728853a2 JMP optimization for GUARDs (guard failur is unexpected) 
TODO: this should be ported to ARM
 2023-02-01 14:51:36 +03:00
Dmitry Stogov
743696fe03 Simplify condition 2023-01-31 16:15:08 +03:00
Dmitry Stogov
038b1e43cd We can't preallocate stack for fastcall function calls 2023-01-31 16:13:15 +03:00
Dmitry Stogov
677c6cb2cb Move declaration of some register alloation related macros to public API 
Use RLOAD.op3 as a flag to avoid spill store
 2023-01-30 16:33:57 +03:00
Dmitry Stogov
4fb50d85aa Add assertion when allocated preserved register is not saved in "fixed" frame prologue 2023-01-26 12:49:23 +03:00
Dmitry Stogov
771da56d07 Fix incorrect tests for empty basic blocks 2023-01-24 11:48:21 +03:00
Dmitry Stogov
a5c0514b13 Use better conditions 2023-01-23 16:05:06 +03:00
Dmitry Stogov
afc948def6 Fix 32-bit negation 2023-01-20 16:00:23 +03:00
Dmitry Stogov
32ad3d1052 Use inline functions to avoid false positive address sanitaizer warnings 2023-01-20 15:35:02 +03:00
Dmitry Stogov
3ac58893f2 Fix address sanitizer warnings 2023-01-20 11:30:22 +03:00
Dmitry Stogov
5103c18269 Fix load fusion in combination with depended register spill load 2023-01-19 13:39:29 +03:00
Dmitry Stogov
208e0040ae Prefer 'ADD [addr], %r1' over 'mov [addr], %r1; lea [%r1, %r2], %r3' 2022-12-28 22:24:42 +03:00
Dmitry Stogov
e067ff66f3 Allow fuse load of constant address 2022-12-28 09:10:16 +03:00
Dmitry Stogov
b043955723 First opernad of IMUL3 can not be constant 2022-12-28 09:09:19 +03:00
Dmitry Stogov
54597bc862 Clear destination regeister before INT to FP conversion to avoid partial register stall 2022-12-28 00:05:23 +03:00
Dmitry Stogov
cc8f3fe987 Fix register allocation for intervals started by RLOAD of non-fixed register. 
These intervals may be split and spilled.
 2022-12-27 22:34:52 +03:00
Dmitry Stogov
d528d29872 Fix memory leaks in case of dynasm errors and JIT buffer overflow 2022-12-26 20:58:54 +03:00
Dmitry Stogov
67da9e93ea Fix register clobbering during argument passing and spill load 2022-12-26 20:25:11 +03:00
Dmitry Stogov
d26b162ffa Fix register clobbering during argument passing 2022-12-26 18:27:53 +03:00
Dmitry Stogov
1df594fea5 Fix memory leak 2022-12-26 14:17:48 +03:00
Dmitry Stogov
cfa8dac9d9 Fix load fusion 2022-12-21 23:32:16 +03:00
Dmitry Stogov
53ead9d2e7 Generate better code for GUARD(_, AND(_, _), _) 2022-12-16 15:07:18 +03:00
Dmitry Stogov
e884e045de Avoid zero extension to the same register 2022-12-16 13:38:58 +03:00
Dmitry Stogov
95729f76bf Use IMUL instead of MUL 2022-12-16 12:57:40 +03:00
Dmitry Stogov
4d7386d342 Fix support for spill loads 2022-12-15 23:27:30 +03:00
Dmitry Stogov
837c59156f Fix support for load fusion of constant address 2022-12-14 13:22:38 +03:00
Dmitry Stogov
47771c73bc Fix inaccurate address fusion 2022-12-13 17:40:08 +03:00
Dmitry Stogov
52842a094a Require temporary register for passing argument through stack 2022-12-12 18:14:31 +03:00
Dmitry Stogov
bfbae48e6f Fix load fusion with spilling 2022-12-09 15:08:43 +03:00
Dmitry Stogov
6790ebf3b5 Implement AFREE instruction to revert ALLOCA 2022-12-07 13:09:00 +03:00
Dmitry Stogov
374df90797 Fix missing sill store 2022-12-07 00:02:02 +03:00
Dmitry Stogov
83d3480391 Fix incorrect spill load inside a fuse load 2022-12-06 23:37:10 +03:00