danog/ir
1
0
Fork 0
mirror of https://github.com/danog/ir.git synced 2024-11-27 04:45:38 +01:00
Code Issues Packages Projects Releases Wiki Activity
277 Commits 2 Branches 0 Tags 3.2 MiB
42df10b3ae
Commit Graph

162 Commits

Author SHA1 Message Date
Dmitry Stogov
8aac74dfb7 Improve code generation 2022-05-26 15:52:42 +03:00
Dmitry Stogov
2917dbbd59 Fix register clobbering 2022-05-26 15:26:04 +03:00
Dmitry Stogov
4862d69609 Improve code generation by load fusing 2022-05-26 14:43:19 +03:00
Dmitry Stogov
4598bd5b12 Better 32/64-bit assertions 2022-05-26 13:37:15 +03:00
Dmitry Stogov
e9fe55faa0 Fix param spill-slot assignment in 32-bit back-end 2022-05-26 13:09:20 +03:00
Dmitry Stogov
e28a3c801e Fix retutn FP numbers for 32-bit x86 back-end 2022-05-26 11:58:51 +03:00
Dmitry Stogov
7e782a291a Extend disassembler to support .rodata section and IP relative data labels 2022-05-26 01:17:02 +03:00
Dmitry Stogov
ead2b69fc6 x86_32 backend (incomplete) 2022-05-25 22:00:18 +03:00
Dmitry Stogov
235c1f2d65 Fix stack parameter loading for x86_32 2022-05-25 15:53:21 +03:00
Dmitry Stogov
341e3b8083 Initial support for x86_32 backend (incomplete) 2022-05-25 14:58:39 +03:00
Dmitry Stogov
9215162833 Ger rid of ir_ctx.bb_num and double neaning of ir_ctx.prev_insn_len 2022-05-25 11:58:35 +03:00
Dmitry Stogov
6f7f7b1268 Implement code generation for type conversion instructions 
Register constraints might need to be tweeked.
 2022-05-20 13:07:41 +03:00
Dmitry Stogov
911219493d Implement IJMP instruction (indirect jump or computed goto) 2022-05-19 18:56:48 +03:00
Dmitry Stogov
bae7df6a5f Implement code generation for MIN and MAX instructions 2022-05-19 17:03:00 +03:00
Dmitry Stogov
8ccb7bc13a Implement overflow checks 2022-05-19 15:49:47 +03:00
Dmitry Stogov
09cee45fd0 Fix compilation warnings 2022-05-19 14:40:57 +03:00
Dmitry Stogov
113b76c867 Add support for instructions that modify result directly in memory for LOAD/STORE 2022-05-19 14:04:29 +03:00
Dmitry Stogov
bf369d0eac Swap operands for better load fusion 2022-05-19 13:17:50 +03:00
Dmitry Stogov
c9bb858e50 Fuse loads without register allocation when this makes sense. 
Make oarameters passed through stack to reuse the same stack slot for spilling.
 2022-05-19 10:53:08 +03:00
Dmitry Stogov
b77f722cb9 cleanup 2022-05-19 09:11:51 +03:00
Dmitry Stogov
177e556754 Fix spill slot comparison 2022-05-18 23:44:59 +03:00
Dmitry Stogov
cdd39f22b0 Merge spills for VSTORE with -O0 2022-05-18 23:12:20 +03:00
Dmitry Stogov
c5a24ff734 Add support for instructions that modify result directly in memory 2022-05-18 21:49:08 +03:00
Dmitry Stogov
2507dde1ad Fix stack alignment 2022-05-18 14:42:03 +03:00
Dmitry Stogov
438c7801cf Fix param offset calculation 2022-05-18 14:36:49 +03:00
Dmitry Stogov
96fc0fb520 Allow passing arguments from MEM to MEM 2022-05-18 10:07:48 +03:00
Dmitry Stogov
efd9ab9a83 cleanup 2022-05-18 00:20:02 +03:00
Dmitry Stogov
5319951060 Align stack once 2022-05-17 23:01:37 +03:00
Dmitry Stogov
e794451451 Preallocate call stack 2022-05-17 22:37:13 +03:00
Dmitry Stogov
445dd65c78 Improve argument passing 2022-05-17 17:30:04 +03:00
Dmitry Stogov
4e917faaba Fix stack parameters loading 2022-05-17 15:00:58 +03:00
Dmitry Stogov
da5de8a390 Introduce IR_PREALLOCATED_STACK flag 2022-05-17 13:15:41 +03:00
Dmitry Stogov
1e7059d7e0 Pass arguments through stack in reverse order 2022-05-17 12:34:31 +03:00
Dmitry Stogov
92ba2fb534 Add support for passing arguments throug stack 
This may be improved by preallocating stack area and
better register allocation.
 2022-05-17 11:20:28 +03:00
Dmitry Stogov
55f21706c9 clenup 2022-05-17 09:09:45 +03:00
Dmitry Stogov
106f201171 Fix support for fixed registers in -O0 register allocator 2022-05-17 08:38:45 +03:00
Dmitry Stogov
fd457e3590 Fix -O0 register allocator 2022-05-17 01:47:44 +03:00
Dmitry Stogov
0189eb28d0 Use a kind of "Buddy Allocaor" to pack spill slots of different sizes 2022-05-17 00:17:59 +03:00
Dmitry Stogov
6fb5380906 Take into account spill slot size and alignment 2022-05-16 22:16:29 +03:00
Dmitry Stogov
8496780ece Fix temporary register usage for parralel arguments passing 2022-05-16 15:34:36 +03:00
Dmitry Stogov
f086da2550 Clenaup (remove unnecessary SHIFT case) 2022-05-16 14:36:27 +03:00
Dmitry Stogov
cebcde2143 Only arguments passed on stack must be in regisers (to avoid mem->mem copy) 2022-05-16 10:50:50 +03:00
Dmitry Stogov
a3b597feef Use different interval for registers clobbered by CALL 2022-05-13 15:53:54 +03:00
Dmitry Stogov
896ddb9e77 Flexable scratch register constraints (allow MUL %edx) 2022-05-13 15:10:15 +03:00
Dmitry Stogov
814d2b4b69 Initial support for indirect calls 
incomplete: live ranges should be adjusted
 2022-05-13 14:38:58 +03:00
Dmitry Stogov
f040444746 Fix incorrect temporary registers intervals for IR_CMP_AND_BRANCH_* 2022-05-13 13:16:31 +03:00
Dmitry Stogov
1f673ebfda Better temporary register usage for SSA deconstruction 2022-05-13 00:32:37 +03:00
Dmitry Stogov
cd00ae6099 Allow spill slot fusing when swap operands of fp comparison 2022-05-12 21:58:58 +03:00
Dmitry Stogov
386b140265 Refactor Linear Scan Register Allocator to use linked lists instead of bitsets 
This fixes allocation of several temporary variables for single instruction
 2022-05-12 17:43:08 +03:00
Dmitry Stogov
d3c4844da7 Fix reading behind array range 2022-05-12 10:57:38 +03:00
Dmitry Stogov
f8edcb9762 Fix possible crash 2022-05-11 18:18:28 +03:00
Dmitry Stogov
2580813c48 cleanup 2022-05-06 19:05:39 +03:00
Dmitry Stogov
69b5a852e5 Make DESSA API use "ir_ref" instead of "virtual register number" 
(0 - is still a temporary register)
 2022-05-06 16:19:57 +03:00
Dmitry Stogov
b2033ebaf9 Fixed parallel copy 2022-05-06 13:32:20 +03:00
Dmitry Stogov
b6ce5055e1 Fix register usage in CALL 2022-05-06 13:12:19 +03:00
Dmitry Stogov
2403fa1edc Fix spill loads during argument passing 2022-05-06 12:55:07 +03:00
Dmitry Stogov
b580c926e6 Avoid need for temporary register for parameters loading 2022-05-06 11:27:24 +03:00
Dmitry Stogov
e434c0a8aa Cleanup and add asserion for unimplemented case 2022-05-06 11:10:09 +03:00
Dmitry Stogov
9d51134813 cleanup 2022-05-06 10:37:25 +03:00
Dmitry Stogov
89f320d7b7 Add SWITCH support for temporary registers 2022-05-06 10:00:19 +03:00
Dmitry Stogov
048ff19133 cleanup 2022-05-05 23:43:16 +03:00
Dmitry Stogov
dd5a3a3b72 Add flexible support for temporary registers. 
Get rid of hardcoded temporary registers (incomplete)
 2022-05-05 22:35:39 +03:00
Dmitry Stogov
4f294109e8 Result of PARAM may be stored into a spill slot without register 2022-05-04 09:50:23 +03:00
Dmitry Stogov
a5b676b590 Fix incorrect operands order 2022-05-04 09:11:05 +03:00
Dmitry Stogov
3e6f84eef4 Add "must be in reg" constraint 2022-04-28 14:48:43 +03:00
Dmitry Stogov
310f605d6c Fix register clobbering 2022-04-26 22:49:41 +03:00
Dmitry Stogov
4a6c8d60a6 Fix ALLOCA to align stack frame 2022-04-22 12:55:38 +03:00
Dmitry Stogov
5cb0af8cd9 Support for compound assignment instructions 2022-04-22 12:11:30 +03:00
Dmitry Stogov
c47de38bab Merge spill slots for VAR, VLOAD and VSTORE (this may be unsafe) 2022-04-22 11:30:33 +03:00
Dmitry Stogov
034ef95e07 Allow memory update instructions (without loading into register) 2022-04-22 01:40:10 +03:00
Dmitry Stogov
ea77ea27cb Improve code for commutative instructions 
(ir_last_use() may be incomplete)
 2022-04-21 21:47:00 +03:00
Dmitry Stogov
c36efda8a5 Improve register allocation for commutative instructions 
- swap operands f this make sense
- fix coalescing bug
 2022-04-21 16:38:18 +03:00
Dmitry Stogov
139b49c6ea Update tasks 2022-04-21 10:20:41 +03:00
Dmitry Stogov
6f3cc3052c Implement ABS for C code generator 
Remove POW
 2022-04-21 01:00:46 +03:00
Dmitry Stogov
506e7b658f Implement ABS and NEG 2022-04-21 00:31:28 +03:00
Dmitry Stogov
a5054f4c31 Add hints for passing arguments 2022-04-20 19:15:03 +03:00
Dmitry Stogov
ffdb53821d Refactor constraint model 
Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE.
Hardware constraints are modeled conectiong live intervals and fixed
intervals to different sub-positions.
 2022-04-20 18:53:15 +03:00
Dmitry Stogov
9d18dd765b Fix stack frame layout 2022-04-20 14:12:52 +03:00
Dmitry Stogov
9796a7d9a4 Fixed stack frame corruption 2022-04-20 12:27:29 +03:00
Dmitry Stogov
705f0f1e1d VADDR instruction 2022-04-20 12:00:36 +03:00
Dmitry Stogov
90e2104fd8 Missing break 2022-04-20 10:02:46 +03:00
Dmitry Stogov
51daf5556c Initial support for ALLOCA, LOAD and STORE (incomplete) 2022-04-19 23:42:05 +03:00
Dmitry Stogov
6b60d8fba9 Code generation for VLOAD and VSTORE 2022-04-19 22:35:29 +03:00
Dmitry Stogov
a1366ebd92 Use zero-extended load if possible 2022-04-19 14:18:39 +03:00
Dmitry Stogov
207dca73e8 64-bit constants support 2022-04-19 14:11:07 +03:00
Dmitry Stogov
ac464ffe5e Support for 64-bit constants in switch 2022-04-19 11:55:12 +03:00
Dmitry Stogov
155c9572c8 Add ability to run "ir_test" with different optimization levels 
Fix JIT for "cmp mem, imm"
 2022-04-19 11:03:01 +03:00
Dmitry Stogov
e327fe2737 Cleanup dessa code 2022-04-19 01:55:11 +03:00
Dmitry Stogov
efe9a96bd2 Cleanup dessa code 2022-04-19 01:28:55 +03:00
Dmitry Stogov
6444a1141a Support for 64-bit constants 2022-04-19 01:02:07 +03:00
Dmitry Stogov
0768bfa60c Initial support for 64-bit constants 2022-04-18 23:26:46 +03:00
Dmitry Stogov
af2919ee5c Suppot for TAILCALL 2022-04-15 16:39:07 +03:00
Dmitry Stogov
f04433999f Reload loading to avoid register clobbering 2022-04-15 15:22:17 +03:00
Dmitry Stogov
3a05363a9d typo 2022-04-14 22:59:00 +03:00
Dmitry Stogov
3f6a6aa3ea Better CPU constraint model and initial support for live interval splitting (incomplete) 2022-04-14 22:40:13 +03:00
Dmitry Stogov
d8e7a8579f Use LEA for 32-bit integers 2022-04-14 18:11:43 +03:00
Dmitry Stogov
c5a39865b0 Use correct function 2022-04-13 21:21:12 +03:00
Dmitry Stogov
1f7a5bcdc7 Switch temporay FP register to %xmm7 2022-04-12 21:57:59 +03:00
Dmitry Stogov
787a443154 Separate common code 2022-04-12 21:53:10 +03:00
Dmitry Stogov
8770d21673 Use parallel copy for arguments passing 2022-04-12 15:08:17 +03:00