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398 Commits

Author SHA1 Message Date
Dmitry Stogov
477dbf7d76 Avoid live range constrction for RLOAD with fixed registers 2023-05-18 13:37:12 +03:00
Dmitry Stogov
c9fa8dfebd Fixed SSA deconstruction 
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
 2023-05-17 22:37:45 +03:00
Dmitry Stogov
842f97cbcb Removed wrong code selection rule 2023-05-11 12:47:49 +03:00
Dmitry Stogov
6f8aa7b540 Add code selection rule to fuse 
movq 0x60(%r14), %rax
    leaq -1(%rax), %rax
    movq %rax, 0x60(%r14)
    testq %rax, %rax
    jle jit$$trace_exit_1

into

    subq $1, 0x60(%r14)
    jle jit$$trace_exit_1"
 2023-05-10 18:22:03 +03:00
Dmitry Stogov
1bbee7b9da Get rid of ir_live_interval.top 2023-04-28 09:49:12 +03:00
Dmitry Stogov
60802d942f Fix previous commit. We still need a temporary register for indirect calls. 2023-04-26 14:10:58 +03:00
Dmitry Stogov
9eb366698d Avoid reservaton of temporary resiser for argument passing 
We may use any scratch register that is not used for parameters
 2023-04-26 12:16:05 +03:00
Dmitry Stogov
0de0c1d0fa Improve parallel copy algorithm to support move of single source into multiple destinations 2023-04-26 10:56:55 +03:00
Dmitry Stogov
1749168078 Add ir_insn_len() and ir_insn_inputs_to_len() private helpers 2023-04-21 13:40:55 +03:00
Dmitry Stogov
e01c43a967 Simplify access to nodes with variable inputs count 2023-04-21 12:40:17 +03:00
Dmitry Stogov
56b0dbccde Use ir_ctx.mflags for CPU specific code-generation options 
'mflags' and ir_cpuinfo() return value have the same meaning.
 2023-04-18 09:54:35 +03:00
Dmitry Stogov
e5c01495da Use arena to allocate live_intervals and nested data structures 2023-04-13 13:47:16 +03:00
Dmitry Stogov
04795b9f04 Fix compilation warnings 2023-04-12 10:48:30 +03:00
Dmitry Stogov
1e5e9e08ce Re-implement instruction fusion and live-range construction 2023-04-05 19:20:43 +03:00
Dmitry Stogov
b109e2f2cd Disable LOAD fusion if there is a STORE or CALL between LOAD and its use 2023-03-30 19:07:21 +03:00
Dmitry Stogov
d79bd88f6f Improve x86 code generation for passing address of label to stack 
-       leal .L1, %eax
-       movl %eax, (%esp)
+       movl $.L1, (%esp)
 2023-03-29 15:48:41 +03:00
Dmitry Stogov
1058cde808 Cleanup instruction selector 2023-03-29 01:21:54 +03:00
Dmitry Stogov
e4b618ad00 Fix fusion of IF(_, CMP(AND(_, _) 0)) 2023-03-28 19:03:06 +03:00
Dmitry Stogov
2cf5f1a7ff typo 2023-03-28 16:59:46 +03:00
Dmitry Stogov
f058ecfc93 Prefer IR_TARGET_* checks instead of system specific macros 2023-03-28 13:40:44 +03:00
Dmitry Stogov
ba0fa44447 Add "const" modifiers 2023-03-28 13:18:12 +03:00
Dmitry Stogov
46f07a8222 Remove unnecessary checks 2023-03-24 00:51:08 +03:00
Dmitry Stogov
72a5649236 Reorder conditions and avoid reloading 2023-03-23 23:44:59 +03:00
Dmitry Stogov
7e687262f7 Remove always true conditions 2023-03-23 22:16:05 +03:00
Dmitry Stogov
87dbdcea0d Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point 2023-03-21 13:45:37 +03:00
Dmitry Stogov
f5b7065b10 Refactor the ENTRY nodes 
Now all ENTRY nodes have a "fake" input control edge.
Through this edge all of them are dominated by START node.
 2023-03-17 09:02:37 +03:00
Dmitry Stogov
6e1848cb40 Add support for Windows TLS 2023-03-07 13:02:44 +03:00
Dmitry Stogov
5e13d47e38 Fix EXITCALL code for WIN64 (support for home/shadow space) 2023-03-07 11:25:22 +03:00
Dmitry Stogov
24f58e7759 Comment assertion to allow PHP/JIT/Win64 work 
Win64 calling convention defines volatile FP registers.
PHP JIT for Win64 saves and restores only GP registers.
This potentionaly may cause register clobbering and unexpected behavior.
 2023-03-03 16:04:54 +03:00
Dmitry Stogov
1542048331 Fix TAILCALL on WIN64 2023-03-02 22:08:24 +03:00
Dmitry Stogov
09d5ecc607 Fix support for WIN64 calling convention 2023-03-02 17:56:15 +03:00
Dmitry Stogov
5a48805c81 Add support for Windows-64 ABI ("home space") 
Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant

TODO: ARM code maight need similar changes
 2023-03-02 13:27:01 +03:00
Dmitry Stogov
e2810c070e Save and restore used non-volatile XMM registers in prologue and epilogue. 
We currently save only "single double" part of the registers using
"movsd" instruction. In general, we should save and restore the whole XMM
registers.
 2023-02-28 18:12:29 +03:00
Dmitry Stogov
eb771b1fef Fix incorrect shift operand 2023-02-28 02:22:09 +03:00
Dmitry Stogov
9b34731d16 Fix most MSVC compilation warnings 2023-02-28 02:11:09 +03:00
Dmitry Stogov
00d5e471ad Improve load fusion, register allocateion and code selection for ADD 2023-02-21 22:55:47 +03:00
Dmitry Stogov
637fe28e90 Add comments 2023-02-21 15:41:41 +03:00
Arnaud Le Blanc
e95cdd0722 Fix temporary register allocation for IR_STORE_INT 
ir_get_target_constraints() mistakenly tests the instruction type and value
instead of the operands'.
 2023-02-18 13:18:49 +01:00
Dmitry Stogov
2f2fed89bb Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32") 2023-02-17 18:11:13 +03:00
Dmitry Stogov
c71076d3f0 Allow reservation stack for passing arguments 2023-02-17 15:52:26 +03:00
Dmitry Stogov
fd653528e9 JMP optimization. Lift constant IJMP targets into jmp_table(s). 2023-02-16 22:41:55 +03:00
Dmitry Stogov
ec8489bf6f Fix spill load 2023-02-16 01:46:16 +03:00
Dmitry Stogov
c7e2cca534 Add hint to reuse register in ZEXT/SEXT 2023-02-15 18:33:02 +03:00
Dmitry Stogov
1d7ab16c2a Allow load fuson for CALL and TAILCALL with arguments 2023-02-14 14:51:12 +03:00
Dmitry Stogov
e19ecd94c3 Eliminate unnecessary "test" or comparison instruction for IF(CMP_OP(BIN_OP(_, _), 0)) 
TODO: this should be ported to ARM
 2023-02-14 11:25:16 +03:00
Dmitry Stogov
6a4187eacc Fixed CLANG build 2023-02-07 23:11:16 +03:00
Dmitry Stogov
d7ed2fdfad We can't relay on block order because they are re-scheduled later 2023-02-07 03:30:44 +03:00
Dmitry Stogov
2e31446e37 Better 'jp' elimination for IR_CMP_AND_BRANCH_FP 2023-02-07 01:57:07 +03:00
Dmitry Stogov
6521c0b7e4 Better 'jp' elimination for GUARDs 2023-02-07 01:06:30 +03:00
Dmitry Stogov
1773bb81aa Make a decision about load fusion and operand swapping together 2023-02-05 14:48:14 +03:00
Dmitry Stogov
cfc959d8ca Better load fusion 2023-02-03 12:50:00 +03:00
Dmitry Stogov
dc728853a2 JMP optimization for GUARDs (guard failur is unexpected) 
TODO: this should be ported to ARM
 2023-02-01 14:51:36 +03:00
Dmitry Stogov
743696fe03 Simplify condition 2023-01-31 16:15:08 +03:00
Dmitry Stogov
038b1e43cd We can't preallocate stack for fastcall function calls 2023-01-31 16:13:15 +03:00
Dmitry Stogov
677c6cb2cb Move declaration of some register alloation related macros to public API 
Use RLOAD.op3 as a flag to avoid spill store
 2023-01-30 16:33:57 +03:00
Dmitry Stogov
4fb50d85aa Add assertion when allocated preserved register is not saved in "fixed" frame prologue 2023-01-26 12:49:23 +03:00
Dmitry Stogov
771da56d07 Fix incorrect tests for empty basic blocks 2023-01-24 11:48:21 +03:00
Dmitry Stogov
a5c0514b13 Use better conditions 2023-01-23 16:05:06 +03:00
Dmitry Stogov
afc948def6 Fix 32-bit negation 2023-01-20 16:00:23 +03:00
Dmitry Stogov
32ad3d1052 Use inline functions to avoid false positive address sanitaizer warnings 2023-01-20 15:35:02 +03:00
Dmitry Stogov
3ac58893f2 Fix address sanitizer warnings 2023-01-20 11:30:22 +03:00
Dmitry Stogov
5103c18269 Fix load fusion in combination with depended register spill load 2023-01-19 13:39:29 +03:00
Dmitry Stogov
208e0040ae Prefer 'ADD [addr], %r1' over 'mov [addr], %r1; lea [%r1, %r2], %r3' 2022-12-28 22:24:42 +03:00
Dmitry Stogov
e067ff66f3 Allow fuse load of constant address 2022-12-28 09:10:16 +03:00
Dmitry Stogov
b043955723 First opernad of IMUL3 can not be constant 2022-12-28 09:09:19 +03:00
Dmitry Stogov
54597bc862 Clear destination regeister before INT to FP conversion to avoid partial register stall 2022-12-28 00:05:23 +03:00
Dmitry Stogov
cc8f3fe987 Fix register allocation for intervals started by RLOAD of non-fixed register. 
These intervals may be split and spilled.
 2022-12-27 22:34:52 +03:00
Dmitry Stogov
d528d29872 Fix memory leaks in case of dynasm errors and JIT buffer overflow 2022-12-26 20:58:54 +03:00
Dmitry Stogov
67da9e93ea Fix register clobbering during argument passing and spill load 2022-12-26 20:25:11 +03:00
Dmitry Stogov
d26b162ffa Fix register clobbering during argument passing 2022-12-26 18:27:53 +03:00
Dmitry Stogov
1df594fea5 Fix memory leak 2022-12-26 14:17:48 +03:00
Dmitry Stogov
cfa8dac9d9 Fix load fusion 2022-12-21 23:32:16 +03:00
Dmitry Stogov
53ead9d2e7 Generate better code for GUARD(_, AND(_, _), _) 2022-12-16 15:07:18 +03:00
Dmitry Stogov
e884e045de Avoid zero extension to the same register 2022-12-16 13:38:58 +03:00
Dmitry Stogov
95729f76bf Use IMUL instead of MUL 2022-12-16 12:57:40 +03:00
Dmitry Stogov
4d7386d342 Fix support for spill loads 2022-12-15 23:27:30 +03:00
Dmitry Stogov
837c59156f Fix support for load fusion of constant address 2022-12-14 13:22:38 +03:00
Dmitry Stogov
47771c73bc Fix inaccurate address fusion 2022-12-13 17:40:08 +03:00
Dmitry Stogov
52842a094a Require temporary register for passing argument through stack 2022-12-12 18:14:31 +03:00
Dmitry Stogov
bfbae48e6f Fix load fusion with spilling 2022-12-09 15:08:43 +03:00
Dmitry Stogov
6790ebf3b5 Implement AFREE instruction to revert ALLOCA 2022-12-07 13:09:00 +03:00
Dmitry Stogov
374df90797 Fix missing sill store 2022-12-07 00:02:02 +03:00
Dmitry Stogov
83d3480391 Fix incorrect spill load inside a fuse load 2022-12-06 23:37:10 +03:00
Dmitry Stogov
0f9d525157 Fix suport for load fusion with constant address 2022-12-05 20:06:42 +03:00
Dmitry Stogov
9a9c6f2aaf Prevent fusion into LEA if operands are reused somewere else 2022-12-01 16:24:20 +03:00
Dmitry Stogov
daf659a457 Fix incorrect conditions 2022-12-01 00:43:42 +03:00
Dmitry Stogov
25ab83e5a3 iBetter address fusion for constant addresses 2022-11-30 18:16:04 +03:00
Dmitry Stogov
6a4e239773 Create a sparate pass to remove unreachableble CFG blocks. 
SCCP pass removes unreachable blocks before CFG construction.
In case of -O0 or -O1 pipeline (without SCCP) it's simpler and faster
to unlink unreachable CFG blocks once, then check for reachability
in almost any compilation pass.
-O2 pipeline (with SCCP) don't need this pass.
 2022-11-29 20:02:07 +03:00
Dmitry Stogov
c9212a1f57 Add missed slot for "fixed" live_intervals for all "scratch" registers 2022-11-22 09:26:25 +03:00
Dmitry Stogov
ef6c59ad8f Avoid instruction selection for the first instructionis of basic blocks 2022-11-18 15:07:19 +03:00
Dmitry Stogov
dde8309108 Use reference to previous instruction instead of its length 2022-11-18 13:59:49 +03:00
Dmitry Stogov
00395f0a23 Cleanup: separate ir_phi_input_number() function 2022-11-18 10:11:16 +03:00
Dmitry Stogov
3e3746d5cb Refactor API that expose target CPU register constraints for register allocator 2022-11-17 23:30:35 +03:00
Dmitry Stogov
118fec9bf7 Fix SNAPSHOT handling 2022-11-16 15:27:34 +03:00
Dmitry Stogov
7015050f22 Simplify CMP_AND_BRANCH and GUARD_CMP via introducing SKIP_CMP rule 2022-11-16 14:09:04 +03:00
Dmitry Stogov
05127b1b13 Remove duplicate code and allow load fusion of IR_SHIFT.op2 2022-11-16 13:20:58 +03:00
Dmitry Stogov
673779ba6a Use IR_COPY_INT/FP rule instead of IR_COPY op 2022-11-16 12:55:40 +03:00
Dmitry Stogov
3535fd2fc4 Fix compilation warnings and signed/unsigned mess 2022-11-08 23:09:35 +03:00
Dmitry Stogov
cc73788981 Fix compilation warnings 2022-11-08 18:17:29 +03:00
Dmitry Stogov
cc56f12f13 Add LICENSE and copyright notices 2022-11-08 11:32:46 +03:00