Dmitry Stogov
c9fa8dfebd
Fixed SSA deconstruction
...
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
2023-05-17 22:37:45 +03:00
Dmitry Stogov
1bbee7b9da
Get rid of ir_live_interval.top
2023-04-28 09:49:12 +03:00
Dmitry Stogov
60802d942f
Fix previous commit. We still need a temporary register for indirect calls.
2023-04-26 14:10:58 +03:00
Dmitry Stogov
9eb366698d
Avoid reservaton of temporary resiser for argument passing
...
We may use any scratch register that is not used for parameters
2023-04-26 12:16:05 +03:00
Dmitry Stogov
0de0c1d0fa
Improve parallel copy algorithm to support move of single source into multiple destinations
2023-04-26 10:56:55 +03:00
Dmitry Stogov
1749168078
Add ir_insn_len() and ir_insn_inputs_to_len() private helpers
2023-04-21 13:40:55 +03:00
Dmitry Stogov
e01c43a967
Simplify access to nodes with variable inputs count
2023-04-21 12:40:17 +03:00
Dmitry Stogov
e5c01495da
Use arena to allocate live_intervals and nested data structures
2023-04-13 13:47:16 +03:00
Dmitry Stogov
04795b9f04
Fix compilation warnings
2023-04-12 10:48:30 +03:00
Dmitry Stogov
1e5e9e08ce
Re-implement instruction fusion and live-range construction
2023-04-05 19:20:43 +03:00
Dmitry Stogov
1058cde808
Cleanup instruction selector
2023-03-29 01:21:54 +03:00
Dmitry Stogov
ba0fa44447
Add "const" modifiers
2023-03-28 13:18:12 +03:00
Dmitry Stogov
72a5649236
Reorder conditions and avoid reloading
2023-03-23 23:44:59 +03:00
Dmitry Stogov
7e687262f7
Remove always true conditions
2023-03-23 22:16:05 +03:00
Dmitry Stogov
87dbdcea0d
Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point
2023-03-21 13:45:37 +03:00
Dmitry Stogov
f5b7065b10
Refactor the ENTRY nodes
...
Now all ENTRY nodes have a "fake" input control edge.
Through this edge all of them are dominated by START node.
2023-03-17 09:02:37 +03:00
Dmitry Stogov
5052a6ca97
Fix stack alignment and allow non-saved permanent registers in the "fixed" frames
2023-03-07 21:38:27 +03:00
Dmitry Stogov
9b34731d16
Fix most MSVC compilation warnings
2023-02-28 02:11:09 +03:00
Dmitry Stogov
637fe28e90
Add comments
2023-02-21 15:41:41 +03:00
Dmitry Stogov
9f81982d86
Fix 'mov' to/from 'sp' register
...
sp is shared with zero register and 'mov' for sp/xzr is encoded differently
2023-02-21 11:42:05 +03:00
Dmitry Stogov
c71076d3f0
Allow reservation stack for passing arguments
2023-02-17 15:52:26 +03:00
Dmitry Stogov
fd653528e9
JMP optimization. Lift constant IJMP targets into jmp_table(s).
2023-02-16 22:41:55 +03:00
Dmitry Stogov
038b1e43cd
We can't preallocate stack for fastcall function calls
2023-01-31 16:13:15 +03:00
Dmitry Stogov
677c6cb2cb
Move declaration of some register alloation related macros to public API
...
Use RLOAD.op3 as a flag to avoid spill store
2023-01-30 16:33:57 +03:00
Dmitry Stogov
bbfcb3e8c8
Fix register allocation for MUL_OV in a different way
2023-01-26 13:20:08 +03:00
Dmitry Stogov
4fb50d85aa
Add assertion when allocated preserved register is not saved in "fixed" frame prologue
2023-01-26 12:49:23 +03:00
Dmitry Stogov
761c50488e
Fix incorrect code generation
2023-01-26 11:50:10 +03:00
Dmitry Stogov
4a67399005
Fix integer MUL overflow checks
2023-01-26 10:08:40 +03:00
Dmitry Stogov
771da56d07
Fix incorrect tests for empty basic blocks
2023-01-24 11:48:21 +03:00
Dmitry Stogov
a5c0514b13
Use better conditions
2023-01-23 16:05:06 +03:00
Dmitry Stogov
32ad3d1052
Use inline functions to avoid false positive address sanitaizer warnings
2023-01-20 15:35:02 +03:00
Dmitry Stogov
3ac58893f2
Fix address sanitizer warnings
2023-01-20 11:30:22 +03:00
Dmitry Stogov
208e0040ae
Prefer 'ADD [addr], %r1' over 'mov [addr], %r1; lea [%r1, %r2], %r3'
2022-12-28 22:24:42 +03:00
Dmitry Stogov
cc8f3fe987
Fix register allocation for intervals started by RLOAD of non-fixed register.
...
These intervals may be split and spilled.
2022-12-27 22:34:52 +03:00
Dmitry Stogov
d528d29872
Fix memory leaks in case of dynasm errors and JIT buffer overflow
2022-12-26 20:58:54 +03:00
Dmitry Stogov
67da9e93ea
Fix register clobbering during argument passing and spill load
2022-12-26 20:25:11 +03:00
Dmitry Stogov
d26b162ffa
Fix register clobbering during argument passing
2022-12-26 18:27:53 +03:00
Dmitry Stogov
9f0bf4849f
Fix build
2022-12-26 14:44:57 +03:00
Dmitry Stogov
1df594fea5
Fix memory leak
2022-12-26 14:17:48 +03:00
Dmitry Stogov
4d7386d342
Fix support for spill loads
2022-12-15 23:27:30 +03:00
Dmitry Stogov
52842a094a
Require temporary register for passing argument through stack
2022-12-12 18:14:31 +03:00
Dmitry Stogov
6790ebf3b5
Implement AFREE instruction to revert ALLOCA
2022-12-07 13:09:00 +03:00
Dmitry Stogov
efbc51baaa
Fixed codegeneration for TRUNC on aarch64
2022-12-07 11:56:53 +03:00
Dmitry Stogov
374df90797
Fix missing sill store
2022-12-07 00:02:02 +03:00
Dmitry Stogov
6a4e239773
Create a sparate pass to remove unreachableble CFG blocks.
...
SCCP pass removes unreachable blocks before CFG construction.
In case of -O0 or -O1 pipeline (without SCCP) it's simpler and faster
to unlink unreachable CFG blocks once, then check for reachability
in almost any compilation pass.
-O2 pipeline (with SCCP) don't need this pass.
2022-11-29 20:02:07 +03:00
Dmitry Stogov
c9212a1f57
Add missed slot for "fixed" live_intervals for all "scratch" registers
2022-11-22 09:26:25 +03:00
Dmitry Stogov
ef6c59ad8f
Avoid instruction selection for the first instructionis of basic blocks
2022-11-18 15:07:19 +03:00
Dmitry Stogov
dde8309108
Use reference to previous instruction instead of its length
2022-11-18 13:59:49 +03:00
Dmitry Stogov
00395f0a23
Cleanup: separate ir_phi_input_number() function
2022-11-18 10:11:16 +03:00
Dmitry Stogov
3e3746d5cb
Refactor API that expose target CPU register constraints for register allocator
2022-11-17 23:30:35 +03:00
Dmitry Stogov
7015050f22
Simplify CMP_AND_BRANCH and GUARD_CMP via introducing SKIP_CMP rule
2022-11-16 14:09:04 +03:00
Dmitry Stogov
673779ba6a
Use IR_COPY_INT/FP rule instead of IR_COPY op
2022-11-16 12:55:40 +03:00
Dmitry Stogov
3535fd2fc4
Fix compilation warnings and signed/unsigned mess
2022-11-08 23:09:35 +03:00
Dmitry Stogov
cc73788981
Fix compilation warnings
2022-11-08 18:17:29 +03:00
Dmitry Stogov
cc56f12f13
Add LICENSE and copyright notices
2022-11-08 11:32:46 +03:00
Dmitry Stogov
d619efa0ad
Add support for ENDBR
2022-10-27 12:58:04 +03:00
Dmitry Stogov
3af9e1a062
Move some common code into ir_emit.c
2022-10-26 22:52:19 +03:00
Dmitry Stogov
1b84570aa3
Intoduce ir_emit.c that shuould keep common part for different targets
2022-10-26 22:06:07 +03:00
Dmitry Stogov
74debb0bf4
Add "ir_load.c" to allow build without llk.php and initial multi-platform support
2022-10-26 19:52:14 +03:00
Dmitry Stogov
9b7835a05e
Use ir_emit_exitgroup() helper API instead of IR_EXITGROUP node
2022-10-26 15:46:59 +03:00
Dmitry Stogov
edd7bc7101
Access ctx->rules[] trough inline function with assertion
...
Fix incorrect accesses
2022-10-26 12:49:34 +03:00
Dmitry Stogov
b99d98979f
Limit CMP+GUARD fusing
2022-10-25 22:09:32 +03:00
Dmitry Stogov
006bee10c7
Add checks for constant references before checking the corresponding rule
2022-10-25 20:36:22 +03:00
Dmitry Stogov
ba90e2825e
SNAPSHOT data shouldn't be in registers
2022-10-25 12:22:49 +03:00
Dmitry Stogov
9f472c1c91
Add support for deoptimization and binding to multiple slots
2022-10-21 17:16:25 +03:00
Dmitry Stogov
81c90972d6
Avoid useless spill stores
2022-10-12 12:09:52 +03:00
Dmitry Stogov
678da7fcc1
Use proper MOV instructions
2022-10-12 12:01:49 +03:00
Dmitry Stogov
0da4b43de8
Fix second argument address
2022-09-29 14:17:54 +03:00
Dmitry Stogov
33bc4ce956
Fixed comparison with zero
2022-09-29 11:31:07 +03:00
Dmitry Stogov
a6e4e988d0
Fix ARM code generator
2022-09-29 02:10:44 +03:00
Dmitry Stogov
494c9225a9
Refactor trace related helpers
2022-09-29 01:25:42 +03:00
Dmitry Stogov
fdaa0cea54
Ignore dead TLS loads
2022-09-28 21:56:10 +03:00
Dmitry Stogov
408b8d2e4b
Fixed support for GUARD/GUARD_NOT
2022-09-27 16:52:15 +03:00
Dmitry Stogov
31220b1de9
Add code generators for missing GUARDs
2022-09-26 20:47:29 +03:00
Dmitry Stogov
63f21925b3
Avoid useless move
2022-09-20 00:26:56 +03:00
Dmitry Stogov
eacb9c1528
Avoid useless mov
2022-09-20 00:12:06 +03:00
Dmitry Stogov
5fdb89aee1
MOD may be converted to AND only for positive op1
2022-09-19 23:22:11 +03:00
Dmitry Stogov
5123080533
Fixed register allocation for MUL_OV
2022-09-19 22:10:29 +03:00
Dmitry Stogov
dc0393320e
Fix floating point comparison
2022-09-19 21:55:08 +03:00
Dmitry Stogov
76ad4e59a6
Fix live range
2022-09-16 12:47:03 +03:00
Dmitry Stogov
0eee478277
Support for always TRUE/FALSE guards
2022-09-16 12:29:55 +03:00
Dmitry Stogov
b519f80da5
More accurte fusion of address calculation
2022-09-16 12:05:36 +03:00
Dmitry Stogov
367e47ac30
Support for preallocated stack (ZEND_VM_HYBRID_JIT_RED_ZONE_SIZE in PHP VM)
2022-09-15 15:39:15 +03:00
Dmitry Stogov
ad59556d85
Add support for binding IR nodes to "external" spill slots (e.g. PHP VM stack slots)
2022-09-15 15:26:43 +03:00
Dmitry Stogov
05bc456c6a
Move base regester selection code into ir_ref_spill_slot()
2022-09-07 23:47:30 +03:00
Dmitry Stogov
2677299bbd
Fix invalid type
2022-09-07 22:21:12 +03:00
Dmitry Stogov
fb0d5fd87c
Improve GUARD instructions support
2022-09-02 13:54:31 +03:00
Dmitry Stogov
756a1afc82
Better register allocation support for address and load fusion
2022-09-01 19:19:01 +03:00
Dmitry Stogov
5e4503b624
Fix JMP optimization for MERGE/N and last basic block
2022-08-31 00:01:15 +03:00
Dmitry Stogov
32198c00b7
Reimplement JMP optimization
2022-08-30 23:15:20 +03:00
Dmitry Stogov
11c03dbfb3
Fix call stack alignment and fastcall support
2022-08-30 00:42:06 +03:00
Dmitry Stogov
47083e0f9f
Improve LOAD fusion
2022-08-25 18:16:17 +03:00
Dmitry Stogov
7513098293
Don't generate code for dead loads
2022-08-23 12:35:10 +03:00
Dmitry Stogov
b0cba142a9
Merge ir_uses_fixed_reg() into ir_get_def_flags() and ir_get_use_flags()
2022-08-12 21:17:19 +03:00
Dmitry Stogov
ca109d3fc9
Use single live interval to handle all scratch registers clobbered by CALL
2022-08-11 19:56:59 +03:00
Dmitry Stogov
36a5bdaf43
Improve support for fixed prologue/epilogue
2022-08-11 13:32:44 +03:00
Dmitry Stogov
1820972a21
Use PHP memory manager
2022-08-10 17:41:14 +03:00
Dmitry Stogov
36561d86ce
Support for negative zero
...
Support for unused CALL result
2022-08-04 00:22:19 +03:00
Dmitry Stogov
88b8731c16
Fix incorrect condition codes
2022-08-02 13:04:03 +03:00
Dmitry Stogov
10db2aeb06
AArch64: Optimize compound assignment to fixed register (RLOAD+ADD+RSTORE)
2022-06-28 16:57:35 +03:00
