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Author SHA1 Message Date
Dmitry Stogov
c93abd79b2 Remove IR_OPND_VAR 2023-05-19 13:00:55 +03:00
Dmitry Stogov
d3640495a2 Ceanup ir_compute_live_ranges() implementation 2023-05-19 12:34:54 +03:00
Dmitry Stogov
5c2023fd7f Avoid live range constrction for VARs 2023-05-18 21:00:57 +03:00
Dmitry Stogov
ef31712f26 Remove usused IR_LIVE_INTERVAL_REG_LOAD flag 2023-05-18 14:17:54 +03:00
Dmitry Stogov
477dbf7d76 Avoid live range constrction for RLOAD with fixed registers 2023-05-18 13:37:12 +03:00
Dmitry Stogov
b6517f2028 Split IR_LIVE_INTERVAL_HAS_HINTS into IR_LIVE_INTERVAL_HAS_HINT_REGS and 
IR_LIVE_INTERVAL_HAS_HINT_REFS
 2023-05-18 10:48:31 +03:00
Dmitry Stogov
3dcb083eb6 Fix Win64 tests 2023-05-17 22:49:26 +03:00
Dmitry Stogov
c9fa8dfebd Fixed SSA deconstruction 
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
 2023-05-17 22:37:45 +03:00
Dmitry Stogov
af7117a3b7 Use cfg_map if available 2023-05-17 11:14:34 +03:00
Dmitry Stogov
aba7818b00 Fixed disassembler output 2023-05-17 09:59:48 +03:00
Dmitry Stogov
2a60d1416d Added missing argument 2023-05-16 13:17:55 +03:00
Dmitry Stogov
e6f642c459 Fix typo and avoid copying of unused tail 2023-05-15 18:06:04 +03:00
Dmitry Stogov
842f97cbcb Removed wrong code selection rule 2023-05-11 12:47:49 +03:00
Dmitry Stogov
6f8aa7b540 Add code selection rule to fuse 
movq 0x60(%r14), %rax
    leaq -1(%rax), %rax
    movq %rax, 0x60(%r14)
    testq %rax, %rax
    jle jit$$trace_exit_1

into

    subq $1, 0x60(%r14)
    jle jit$$trace_exit_1"
 2023-05-10 18:22:03 +03:00
Dmitry Stogov
c6b5075733
Merge pull request #31 from stkeke/trivial_fix 
A serial of trivial fixes in source code
 2023-05-10 14:52:50 +03:00
Tony Su
5302cdf8ee [ir_load]: Make report_undefined_var() static 
It looks like report_undefined_var() is only used in ir_load.c and no
other places. Make it static.

Signed-off-by: Tony Su <tao.su@intel.com>
 2023-05-10 19:41:18 +08:00
Tony Su
f005199576 [ir.h]: Put comment in correct place 
It looks like the comment for IR constant value accidentally is misplaced.

Signed-off-by: Tony Su <tao.su@intel.com>
 2023-05-10 19:41:18 +08:00
Tony Su
a2d1d57a80 [ir_strtab]: Make ir_str_hash() static 
This function is not used outside ir_strtab.c source file,
hence make it static.

Signed-off-by: Tony Su <tao.su@intel.com>
 2023-05-10 19:41:18 +08:00
Tony Su
42882d18f1 [ir_main]: print default optimization level in help message 
At first, I had thought optimization is disabled without -O option, in
fact, the default level is 2 and let's make it clear in --help message.

Signed-off-by: Tony Su <tao.su@intel.com>
 2023-05-10 19:41:18 +08:00
Tony Su
007856ffd6 [Bug]: Fix target CPU AVX availability check logic 
Use && instead of & to make the checking logic clear.
Keep flag in error message compatible with --help message.

Signed-off-by: Tony Su <tao.su@intel.com>
 2023-05-10 19:41:18 +08:00
Dmitry Stogov
c13fbacd20
Merge pull request #28 from jserv/fix-linkage 
Fix linkage to libdl
 2023-05-10 10:30:48 +03:00
Jim Huang
90945934c1 Fix linkage to libdl 
This patch resolves undefined reference to symbols in libdl.

Error message before this:
  /usr/bin/ld: ir_emit.o: in function `ir_resolve_sym_name':
  ir_emit.c:249: undefined reference to `dlsym'
  /usr/bin/ld: ir_disasm.o: in function `ir_disasm_resolver':
  ir_disasm.c:302: undefined reference to `dladdr'
  collect2: error: ld returned 1 exit status
 2023-05-08 00:26:45 +08:00
Dmitry Stogov
d859591943 Inline fast path 2023-05-05 18:37:14 +03:00
Dmitry Stogov
c3fca224ff Introduce IR_OP_FLAG_PINNED and IR_BB_HAS_PHI/PI/PARAM/VAR flags 2023-05-05 16:59:22 +03:00
Dmitry Stogov
1150c80ca2 Fixed support for OSR ENTRY 2023-05-05 12:59:33 +03:00
Dmitry Stogov
76f44fa126 Implemented path-exploration based live ranges construction 
The algorithm is based on "Computing Liveness Sets for SSA-Form Programs",
Florian Brandner, Benoit Boissinot, Alain Darte, Benoit Dupont de Dinechin,
Fabrice Rastello. TR Inria RR-7503, 2011

In comparison to the existing bitset based approach, the new algorithm
is more memory-space efficient and faster on big functions.
 2023-05-05 02:01:53 +03:00
Dmitry Stogov
ac3a11e911 Improve ir_add_live_range(). Set ival->type when process definition. 2023-05-04 12:23:40 +03:00
Dmitry Stogov
47b0bb0789 Remove useless memset() 2023-05-04 01:31:34 +03:00
Dmitry Stogov
d30f523c62 Avoid iteration over an empty bitset 2023-05-03 12:30:05 +03:00
Dmitry Stogov
1bbee7b9da Get rid of ir_live_interval.top 2023-04-28 09:49:12 +03:00
Dmitry Stogov
23bbdd7ceb Avoid loop nesting forest consruction if we didn't detect loops in ir_build_dominators_tree() 2023-04-27 18:00:30 +03:00
Dmitry Stogov
367d2e3246 Avoid CFG reachability check after SCCP 
SCCP eliminates unreachable BBs before the CFG constraction.
So ir_build_cfg() doesn't need to perforem reachability chececk if it
runs after SCCP, otherwise it starts call ir_remove_unreachable_blocks() if necessary.
User code dont have to call ir_remove_unreachable_blocks() anymore.
 2023-04-27 14:18:39 +03:00
Dmitry Stogov
b15d9d213f Use a faster dominator tree construction algorithm that relays on required IR BB order 2023-04-27 11:49:21 +03:00
Dmitry Stogov
53f4435f8e Fixed test 2023-04-26 14:24:43 +03:00
Dmitry Stogov
60802d942f Fix previous commit. We still need a temporary register for indirect calls. 2023-04-26 14:10:58 +03:00
Dmitry Stogov
9eb366698d Avoid reservaton of temporary resiser for argument passing 
We may use any scratch register that is not used for parameters
 2023-04-26 12:16:05 +03:00
Dmitry Stogov
0de0c1d0fa Improve parallel copy algorithm to support move of single source into multiple destinations 2023-04-26 10:56:55 +03:00
Dmitry Stogov
c2470bc684 Disable LICM across an OSR ENTRY if the value can't be restored at OSR ENTRY point (support for nested loops) 2023-04-25 21:54:30 +03:00
Dmitry Stogov
7441eb2171 Limit Alias Analyses (search above address doesn't make sense) 2023-04-25 14:35:20 +03:00
Dmitry Stogov
342be9c5c6 Prevent "dead" STORE elimination in case there is a GUARD beteen two STOREs 2023-04-25 13:58:27 +03:00
Dmitry Stogov
20d3a4fac1
Merge pull request #26 from stkeke/show_diff_win 
[ir-test]: Fix #25: use 'fc.exe' for diff on Windows
 2023-04-25 09:22:57 +03:00
Tony Su
66c07b8cc7 [ir-test]: Fix #25: use 'fc.exe' for diff on Windows 
Fix: https://github.com/dstogov/ir/issues/25

> nmake.exe -f .\win32\Makefile test-ci

001.irt is specially changed for test to fail.
FAIL: 001: add function [.\tests\001.irt]
Comparing files .\TESTS\001.exp and .\TESTS\001.OUT
***** .\TESTS\001.exp
    1:  {
    2:          uintptr_t c_1 = 1;
    3:          bool c_2 = 0;
***** .\TESTS\001.OUT
    1:  {
    2:          uintptr_t c_1 = 0;
    3:          bool c_2 = 0;
*****

Signed-off-by: Tony Su <tao.su@intel.com>
 2023-04-23 10:38:39 +08:00
Dmitry Stogov
1749168078 Add ir_insn_len() and ir_insn_inputs_to_len() private helpers 2023-04-21 13:40:55 +03:00
Dmitry Stogov
e01c43a967 Simplify access to nodes with variable inputs count 2023-04-21 12:40:17 +03:00
Dmitry Stogov
683f8d2124
Merge pull request #24 from stkeke/enhence_ir-test 
Enhance ir test framework
 2023-04-19 15:02:11 +03:00
Tony Su
4b9391c8b1 [ir-test]: Enhance ir-test for Linux and Windows 
This is a series of enhancements for ir-test and related Makefile
for Linux and Windows.

UpdateLog:
1) Make ir-test run from any directory
2) add --help option and print program usage
3) Enable user to specify test folders and/or files to run
4) Check unsupported option and print help usage
5) Update Makefile to use new ir-test options
6) some code refactory

Signed-off-by: Tony Su <tao.su@intel.com>
Reviewed-by  : Dmitry Stogov
Reviewed-by  : Anatol Belski
 2023-04-19 19:33:36 +08:00
Dmitry Stogov
1f7a2bd243 Remove useless "AVX" tests for AArch64 2023-04-18 10:14:59 +03:00
Dmitry Stogov
bcf6c2f152 Set 'mflags' default value 2023-04-18 09:59:41 +03:00
Dmitry Stogov
56b0dbccde Use ir_ctx.mflags for CPU specific code-generation options 
'mflags' and ir_cpuinfo() return value have the same meaning.
 2023-04-18 09:54:35 +03:00
Dmitry Stogov
d26099c5ac
Merge pull request #21 from weltling/cpuid 
[RFC] cpu: Add framework for CPU feature handling
 2023-04-17 10:35:29 +03:00