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164 Commits 2 Branches 0 Tags
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42 Commits

Author SHA1 Message Date
Dmitry Stogov
c9bb858e50 Fuse loads without register allocation when this makes sense. 
Make oarameters passed through stack to reuse the same stack slot for spilling.
 2022-05-19 10:53:08 +03:00
Dmitry Stogov
c5a24ff734 Add support for instructions that modify result directly in memory 2022-05-18 21:49:08 +03:00
Dmitry Stogov
96fc0fb520 Allow passing arguments from MEM to MEM 2022-05-18 10:07:48 +03:00
Dmitry Stogov
e794451451 Preallocate call stack 2022-05-17 22:37:13 +03:00
Dmitry Stogov
f08386b379 Update tasks 2022-05-17 15:04:32 +03:00
Dmitry Stogov
3e5f151502 Update tasks 2022-05-17 00:21:00 +03:00
Dmitry Stogov
49374df65c Remove done and outdated tasks 2022-05-16 15:38:25 +03:00
Dmitry Stogov
8496780ece Fix temporary register usage for parralel arguments passing 2022-05-16 15:34:36 +03:00
Dmitry Stogov
5f529a9d67 Hint propagation 2022-05-16 11:53:10 +03:00
Dmitry Stogov
f040444746 Fix incorrect temporary registers intervals for IR_CMP_AND_BRANCH_* 2022-05-13 13:16:31 +03:00
Dmitry Stogov
8895b18c0c Added task 2022-05-13 09:06:43 +03:00
Dmitry Stogov
1f673ebfda Better temporary register usage for SSA deconstruction 2022-05-13 00:32:37 +03:00
Dmitry Stogov
dd5a3a3b72 Add flexible support for temporary registers. 
Get rid of hardcoded temporary registers (incomplete)
 2022-05-05 22:35:39 +03:00
Dmitry Stogov
1130c256ae Find optimal split position 2022-05-04 11:59:35 +03:00
Dmitry Stogov
3e6f84eef4 Add "must be in reg" constraint 2022-04-28 14:48:43 +03:00
Dmitry Stogov
240259adf8 add task 2022-04-28 09:23:02 +03:00
Dmitry Stogov
99e2b4c3fd Remove done and add new tasks 2022-04-22 13:31:28 +03:00
Dmitry Stogov
4a6c8d60a6 Fix ALLOCA to align stack frame 2022-04-22 12:55:38 +03:00
Dmitry Stogov
5cb0af8cd9 Support for compound assignment instructions 2022-04-22 12:11:30 +03:00
Dmitry Stogov
ea77ea27cb Improve code for commutative instructions 
(ir_last_use() may be incomplete)
 2022-04-21 21:47:00 +03:00
Dmitry Stogov
139b49c6ea Update tasks 2022-04-21 10:20:41 +03:00
Dmitry Stogov
6f3cc3052c Implement ABS for C code generator 
Remove POW
 2022-04-21 01:00:46 +03:00
Dmitry Stogov
506e7b658f Implement ABS and NEG 2022-04-21 00:31:28 +03:00
Dmitry Stogov
705f0f1e1d VADDR instruction 2022-04-20 12:00:36 +03:00
Dmitry Stogov
81852e6536 Separate tasks 2022-04-20 10:03:00 +03:00
Dmitry Stogov
51daf5556c Initial support for ALLOCA, LOAD and STORE (incomplete) 2022-04-19 23:42:05 +03:00
Dmitry Stogov
6b60d8fba9 Code generation for VLOAD and VSTORE 2022-04-19 22:35:29 +03:00
Dmitry Stogov
7e9d1d7dba Improve VLOAD/VSTORE support in C code generator 2022-04-19 17:14:44 +03:00
Dmitry Stogov
a1366ebd92 Use zero-extended load if possible 2022-04-19 14:18:39 +03:00
Dmitry Stogov
207dca73e8 64-bit constants support 2022-04-19 14:11:07 +03:00
Dmitry Stogov
ac464ffe5e Support for 64-bit constants in switch 2022-04-19 11:55:12 +03:00
Dmitry Stogov
e327fe2737 Cleanup dessa code 2022-04-19 01:55:11 +03:00
Dmitry Stogov
6444a1141a Support for 64-bit constants 2022-04-19 01:02:07 +03:00
Dmitry Stogov
0768bfa60c Initial support for 64-bit constants 2022-04-18 23:26:46 +03:00
Dmitry Stogov
ff887eaf49 comment 2022-04-15 16:44:12 +03:00
Dmitry Stogov
3cb707522f Allocate scratch (caller-saved) registers first 2022-04-15 14:22:35 +03:00
Dmitry Stogov
6b0c4435c2 Separate tasks 2022-04-14 23:03:30 +03:00
Dmitry Stogov
58c80c48e0 Create fixed interval for a temporary register used for DESSA moves 2022-04-12 16:09:53 +03:00
Dmitry Stogov
8770d21673 Use parallel copy for arguments passing 2022-04-12 15:08:17 +03:00
Dmitry Stogov
63e1c0fc87 Update TODO 2022-04-12 10:37:20 +03:00
Dmitry Stogov
9ccefcf973 Support for more instruction in C backend and BOOL_NOT in x86_86 2022-04-08 19:02:11 +03:00
Dmitry Stogov
f1cc9a4ddb Added tests for unary integer instructions 2022-04-08 16:40:28 +03:00