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374 Commits

Author SHA1 Message Date
Dmitry Stogov
95729f76bf Use IMUL instead of MUL 2022-12-16 12:57:40 +03:00
Dmitry Stogov
4d7386d342 Fix support for spill loads 2022-12-15 23:27:30 +03:00
Dmitry Stogov
837c59156f Fix support for load fusion of constant address 2022-12-14 13:22:38 +03:00
Dmitry Stogov
47771c73bc Fix inaccurate address fusion 2022-12-13 17:40:08 +03:00
Dmitry Stogov
52842a094a Require temporary register for passing argument through stack 2022-12-12 18:14:31 +03:00
Dmitry Stogov
bfbae48e6f Fix load fusion with spilling 2022-12-09 15:08:43 +03:00
Dmitry Stogov
6790ebf3b5 Implement AFREE instruction to revert ALLOCA 2022-12-07 13:09:00 +03:00
Dmitry Stogov
374df90797 Fix missing sill store 2022-12-07 00:02:02 +03:00
Dmitry Stogov
83d3480391 Fix incorrect spill load inside a fuse load 2022-12-06 23:37:10 +03:00
Dmitry Stogov
0f9d525157 Fix suport for load fusion with constant address 2022-12-05 20:06:42 +03:00
Dmitry Stogov
9a9c6f2aaf Prevent fusion into LEA if operands are reused somewere else 2022-12-01 16:24:20 +03:00
Dmitry Stogov
daf659a457 Fix incorrect conditions 2022-12-01 00:43:42 +03:00
Dmitry Stogov
25ab83e5a3 iBetter address fusion for constant addresses 2022-11-30 18:16:04 +03:00
Dmitry Stogov
6a4e239773 Create a sparate pass to remove unreachableble CFG blocks. 
SCCP pass removes unreachable blocks before CFG construction.
In case of -O0 or -O1 pipeline (without SCCP) it's simpler and faster
to unlink unreachable CFG blocks once, then check for reachability
in almost any compilation pass.
-O2 pipeline (with SCCP) don't need this pass.
 2022-11-29 20:02:07 +03:00
Dmitry Stogov
c9212a1f57 Add missed slot for "fixed" live_intervals for all "scratch" registers 2022-11-22 09:26:25 +03:00
Dmitry Stogov
ef6c59ad8f Avoid instruction selection for the first instructionis of basic blocks 2022-11-18 15:07:19 +03:00
Dmitry Stogov
dde8309108 Use reference to previous instruction instead of its length 2022-11-18 13:59:49 +03:00
Dmitry Stogov
00395f0a23 Cleanup: separate ir_phi_input_number() function 2022-11-18 10:11:16 +03:00
Dmitry Stogov
3e3746d5cb Refactor API that expose target CPU register constraints for register allocator 2022-11-17 23:30:35 +03:00
Dmitry Stogov
118fec9bf7 Fix SNAPSHOT handling 2022-11-16 15:27:34 +03:00
Dmitry Stogov
7015050f22 Simplify CMP_AND_BRANCH and GUARD_CMP via introducing SKIP_CMP rule 2022-11-16 14:09:04 +03:00
Dmitry Stogov
05127b1b13 Remove duplicate code and allow load fusion of IR_SHIFT.op2 2022-11-16 13:20:58 +03:00
Dmitry Stogov
673779ba6a Use IR_COPY_INT/FP rule instead of IR_COPY op 2022-11-16 12:55:40 +03:00
Dmitry Stogov
3535fd2fc4 Fix compilation warnings and signed/unsigned mess 2022-11-08 23:09:35 +03:00
Dmitry Stogov
cc73788981 Fix compilation warnings 2022-11-08 18:17:29 +03:00
Dmitry Stogov
cc56f12f13 Add LICENSE and copyright notices 2022-11-08 11:32:46 +03:00
Dmitry Stogov
d619efa0ad Add support for ENDBR 2022-10-27 12:58:04 +03:00
Dmitry Stogov
3af9e1a062 Move some common code into ir_emit.c 2022-10-26 22:52:19 +03:00
Dmitry Stogov
1b84570aa3 Intoduce ir_emit.c that shuould keep common part for different targets 2022-10-26 22:06:07 +03:00
Dmitry Stogov
9b7835a05e Use ir_emit_exitgroup() helper API instead of IR_EXITGROUP node 2022-10-26 15:46:59 +03:00
Dmitry Stogov
2dea40bfab Add API to patch native code 2022-10-26 13:44:44 +03:00
Dmitry Stogov
edd7bc7101 Access ctx->rules[] trough inline function with assertion 
Fix incorrect accesses
 2022-10-26 12:49:34 +03:00
Dmitry Stogov
b99d98979f Limit CMP+GUARD fusing 2022-10-25 22:09:32 +03:00
Dmitry Stogov
006bee10c7 Add checks for constant references before checking the corresponding rule 2022-10-25 20:36:22 +03:00
Dmitry Stogov
ba90e2825e SNAPSHOT data shouldn't be in registers 2022-10-25 12:22:49 +03:00
Dmitry Stogov
9f472c1c91 Add support for deoptimization and binding to multiple slots 2022-10-21 17:16:25 +03:00
Dmitry Stogov
6667b7efae Fix register allocation (one of operands MUST be in a register) 2022-10-21 12:02:31 +03:00
Dmitry Stogov
3d175e1576 Fix fuse load 2022-10-18 13:53:00 +03:00
Dmitry Stogov
81c90972d6 Avoid useless spill stores 2022-10-12 12:09:52 +03:00
Dmitry Stogov
678da7fcc1 Use proper MOV instructions 2022-10-12 12:01:49 +03:00
Dmitry Stogov
db8a80e8d5 Temporary remove "pxor". 
It should be added before all "cvt*" instructions
 2022-09-29 20:05:00 +03:00
Dmitry Stogov
0da4b43de8 Fix second argument address 2022-09-29 14:17:54 +03:00
Dmitry Stogov
33bc4ce956 Fixed comparison with zero 2022-09-29 11:31:07 +03:00
Dmitry Stogov
494c9225a9 Refactor trace related helpers 2022-09-29 01:25:42 +03:00
Dmitry Stogov
fdaa0cea54 Ignore dead TLS loads 2022-09-28 21:56:10 +03:00
Dmitry Stogov
a1361d77ba Support for calling FASTCALL variable functions. 
Currutly this done through BITCAST hack.
It may make sense to implement full support for function prototypes.
 2022-09-28 20:48:35 +03:00
Dmitry Stogov
924f5949f2 Fixed SSE operands alignment and 32-bit support 2022-09-27 20:36:34 +03:00
Dmitry Stogov
408b8d2e4b Fixed support for GUARD/GUARD_NOT 2022-09-27 16:52:15 +03:00
Dmitry Stogov
31220b1de9 Add code generators for missing GUARDs 2022-09-26 20:47:29 +03:00
Dmitry Stogov
da11454058 Fix incorrect code for IJMP 2022-09-26 14:45:12 +03:00
Dmitry Stogov
2b4a7d2cb3 Fix out of bounds array access 2022-09-23 12:36:11 +03:00
Dmitry Stogov
8f5768628a Initial support for tracing JIT 2022-09-23 12:22:59 +03:00
Dmitry Stogov
05fd1f971d Better LOAD fusion 2022-09-21 23:54:45 +03:00
Dmitry Stogov
12c183f391 Added support for GUARD_OVERFLOW 2022-09-20 17:38:27 +03:00
Dmitry Stogov
c186fb2c25 Fix constant address loading 2022-09-20 14:37:10 +03:00
Dmitry Stogov
63f21925b3 Avoid useless move 2022-09-20 00:26:56 +03:00
Dmitry Stogov
eacb9c1528 Avoid useless mov 2022-09-20 00:12:06 +03:00
Dmitry Stogov
b519f80da5 More accurte fusion of address calculation 2022-09-16 12:05:36 +03:00
Dmitry Stogov
86bec14bc2 Fixed fuse loading in BITCAST 2022-09-16 10:19:31 +03:00
Dmitry Stogov
4a8ebd5be5 Fuse function address load into CALL/TAILCALL without arguments 2022-09-16 09:54:49 +03:00
Dmitry Stogov
57a9731179 Fix spill load code 2022-09-15 23:24:28 +03:00
Dmitry Stogov
b549d98aba The second operand for MEM_BINOP_INT must be in a register 2022-09-15 20:29:30 +03:00
Dmitry Stogov
367e47ac30 Support for preallocated stack (ZEND_VM_HYBRID_JIT_RED_ZONE_SIZE in PHP VM) 2022-09-15 15:39:15 +03:00
Dmitry Stogov
ad59556d85 Add support for binding IR nodes to "external" spill slots (e.g. PHP VM stack slots) 2022-09-15 15:26:43 +03:00
Dmitry Stogov
5f4b42155f ctx->rules[] is valid only for non CONST IR reference 2022-09-14 15:54:24 +03:00
Dmitry Stogov
05bc456c6a Move base regester selection code into ir_ref_spill_slot() 2022-09-07 23:47:30 +03:00
Dmitry Stogov
2677299bbd Fix invalid type 2022-09-07 22:21:12 +03:00
Dmitry Stogov
b68c4db601 Don't fuse LOAD into instruction in diffrent basic block 2022-09-06 14:01:35 +03:00
Dmitry Stogov
8600801c1f Eliminate identical comparisons 2022-09-05 14:41:38 +03:00
Dmitry Stogov
fb0d5fd87c Improve GUARD instructions support 2022-09-02 13:54:31 +03:00
Dmitry Stogov
c865599451 Fix code generation 2022-09-02 13:12:58 +03:00
Dmitry Stogov
5034f8dedb Allow genearion of TEST MEM, IMM 2022-09-01 22:25:29 +03:00
Dmitry Stogov
9b558e544f Allow fusion of single address calculation instruction into several load/store instructions 
Previously, if calculated address were used in few places we kept it in a register (without
fusion).
 2022-09-01 20:40:29 +03:00
Dmitry Stogov
756a1afc82 Better register allocation support for address and load fusion 2022-09-01 19:19:01 +03:00
Dmitry Stogov
5e4503b624 Fix JMP optimization for MERGE/N and last basic block 2022-08-31 00:01:15 +03:00
Dmitry Stogov
32198c00b7 Reimplement JMP optimization 2022-08-30 23:15:20 +03:00
Dmitry Stogov
5afa116d34 Get rid of MREF macros 2022-08-30 16:15:30 +03:00
Dmitry Stogov
80192093e5 Swap operands of FP comparison to produce the better code 2022-08-30 15:52:55 +03:00
Dmitry Stogov
e4be1de649 Allow LOAD/STORE fusion for ADD_OV/SUB_OV 2022-08-30 12:23:20 +03:00
Dmitry Stogov
0596de2291 Fuse LOAD into IMULL/3 2022-08-30 11:26:38 +03:00
Dmitry Stogov
e87e71b092 cleanup 2022-08-30 10:23:56 +03:00
Dmitry Stogov
11c03dbfb3 Fix call stack alignment and fastcall support 2022-08-30 00:42:06 +03:00
Dmitry Stogov
fd8539e17d Eliminate TEST after ADD/SUB/AND/OR/XOR 2022-08-29 22:22:30 +03:00
Dmitry Stogov
c69d970ca2 Add missing "else" 2022-08-26 11:50:28 +03:00
Dmitry Stogov
e023a18749 Test part of the register to avoid test with mask 2022-08-26 11:48:13 +03:00
Dmitry Stogov
57f9e6ed8f Optimize AND into TEST 2022-08-26 11:07:35 +03:00
Dmitry Stogov
23d7b3b4ac Simplift integer comarison code genertor 2022-08-25 23:42:15 +03:00
Dmitry Stogov
1d4b00ddb0 Load fusion for BITCAST 2022-08-25 23:18:00 +03:00
Dmitry Stogov
f8cf71318e Load fusion into type conversion instructions 2022-08-25 23:06:45 +03:00
Dmitry Stogov
56956cbe0f Load fusion for IF_INT 2022-08-25 22:18:15 +03:00
Dmitry Stogov
1f657fd4d7 Load fusion for MUL/DIV/MOD 2022-08-25 21:47:07 +03:00
Dmitry Stogov
dbb382224d Remove useless code 2022-08-25 21:14:56 +03:00
Dmitry Stogov
47083e0f9f Improve LOAD fusion 2022-08-25 18:16:17 +03:00
Dmitry Stogov
aa28e865da Fuse load into binary ops 2022-08-24 23:26:08 +03:00
Dmitry Stogov
65e1619de8 Fuse address calculation into LOAD/STORE 2022-08-24 16:11:04 +03:00
Dmitry Stogov
7513098293 Don't generate code for dead loads 2022-08-23 12:35:10 +03:00
Dmitry Stogov
b0cba142a9 Merge ir_uses_fixed_reg() into ir_get_def_flags() and ir_get_use_flags() 2022-08-12 21:17:19 +03:00
Dmitry Stogov
ca109d3fc9 Use single live interval to handle all scratch registers clobbered by CALL 2022-08-11 19:56:59 +03:00
Dmitry Stogov
36a5bdaf43 Improve support for fixed prologue/epilogue 2022-08-11 13:32:44 +03:00
Dmitry Stogov
1820972a21 Use PHP memory manager 2022-08-10 17:41:14 +03:00
Dmitry Stogov
901e1de968 Fix incorrect code selection pattern 2022-08-09 21:54:34 +03:00
Dmitry Stogov
66458b4dee Add spill code 2022-08-08 23:17:33 +03:00
Dmitry Stogov
36561d86ce Support for negative zero 
Support for unused CALL result
 2022-08-04 00:22:19 +03:00
Dmitry Stogov
88b8731c16 Fix incorrect condition codes 2022-08-02 13:04:03 +03:00
Dmitry Stogov
6c78558bfe Fuse address calculation into FP load/store 2022-07-26 21:04:26 +03:00
Dmitry Stogov
1e5ce07406 Fix int32_t overflow 2022-07-26 20:29:06 +03:00
Dmitry Stogov
ac8b3bac28 Allow GUARDs with constant conditions 2022-07-22 09:45:52 +03:00
Dmitry Stogov
1089699f2c Only unsigned MOD may be converted into AND 2022-07-21 20:45:19 +03:00
Dmitry Stogov
e235a33679 Fix negaive DIV/MOD 2022-07-21 20:39:36 +03:00
Dmitry Stogov
6800af4013 Support for IJMP with constant operand 2022-07-21 20:25:19 +03:00
Dmitry Stogov
efbc6d6b84 Fix address calculation fusion 2022-07-20 22:30:25 +03:00
Dmitry Stogov
3c4135576a Add TRAP instruction 2022-07-20 17:59:44 +03:00
Dmitry Stogov
42df10b3ae Fuse address calculation into store 2022-07-20 17:19:46 +03:00
Dmitry Stogov
4004a9d222 Support for overflow detection 2022-07-20 11:25:53 +03:00
Dmitry Stogov
e1ae79102a Fuse address calulation with the following binary op 2022-07-19 17:53:17 +03:00
Dmitry Stogov
6b92f02a9c AArch64: Fuse address calculation into LDR/STR instructions 2022-06-28 12:24:50 +03:00
Dmitry Stogov
b6605500f0 Improve AArch64 support 2022-06-28 01:43:59 +03:00
Dmitry Stogov
907c22261d Turn IR_TLS into "load" 2022-06-28 00:03:06 +03:00
Dmitry Stogov
fe333adfa1 Add ability to force fix/restore some predefied registers 2022-06-23 22:39:00 +03:00
Dmitry Stogov
c9fa87e6c4 Support for fastcall caling convention. 
(this should be reimplemented through function prototypes)
 2022-06-23 13:14:30 +03:00
Dmitry Stogov
56c8b372a8 Replace ir_insn.emit_const by ir_insn.const_flags 2022-06-23 11:25:47 +03:00
Dmitry Stogov
2148f05392 Initial support for fascall calling convention (incomplete) 2022-06-22 23:59:56 +03:00
Dmitry Stogov
ef3ffff81b Fix CALL/1 copying. Fallback to CALL+RETURN when we can't generate code for TAILCALL. 2022-06-22 17:57:31 +03:00
Dmitry Stogov
a165c43196 Initial support for thread local storage + optimization of some related code selection patterns 2022-06-22 16:02:43 +03:00
Dmitry Stogov
9b25587eb6 Compound assignment instruction fusion 2022-06-21 17:33:57 +03:00
Dmitry Stogov
cb64f578eb Avoid memory allocation for empty arguments list 2022-06-21 13:04:33 +03:00
Dmitry Stogov
00e92483bc Fix compilation warnings 2022-06-21 11:41:59 +03:00
Dmitry Stogov
5ef1e97261 Better support for unreachable basic blocks 2022-06-20 16:34:44 +03:00
Dmitry Stogov
f8a23e9fe4 Don't protect/unprotect external code buffer 2022-06-17 13:22:26 +03:00
Dmitry Stogov
411dd20331 Support for code fragments with multiple entries 2022-06-16 23:49:27 +03:00
Dmitry Stogov
5fb115ab11 Remove LOOP_EXIT 2022-06-15 17:27:31 +03:00
Dmitry Stogov
706850f578 Prevent mov reg to itself 2022-06-15 14:37:16 +03:00
Dmitry Stogov
d877e35909 Fuse load+cmp 2022-06-15 13:15:19 +03:00
Dmitry Stogov
b5a3b2fe90 Load fusion and cmp+guard fusion 2022-06-15 12:27:36 +03:00
Dmitry Stogov
be0ecd0eb8 Fix LOAD/STORE with constant addresses 2022-06-14 22:38:35 +03:00
Dmitry Stogov
0a93d2e41b Fix incorrect type usage 2022-06-14 20:51:39 +03:00
Dmitry Stogov
f841fb6c34 Initial support for guards 2022-06-14 16:27:33 +03:00
Dmitry Stogov
af4558e439 Allow emitting native code into preallocated buffer 2022-06-10 11:30:19 +03:00
Dmitry Stogov
5cafe50d36 Initial support for PHP 2022-06-10 00:16:29 +03:00
Dmitry Stogov
63ec9b4864 iRemove useless (always true) condition 2022-06-07 14:45:57 +03:00
Dmitry Stogov
fbedabc5d8 cleanup 2022-06-07 10:17:41 +03:00
Dmitry Stogov
1108acf9b8 cleanup 2022-06-06 23:12:45 +03:00
Dmitry Stogov
ad052c59ab cleanup 2022-06-06 22:36:11 +03:00
Dmitry Stogov
17797a4a84 cleanup 2022-06-06 18:10:41 +03:00
Dmitry Stogov
f6b81b14e9 Aarch64 back-end 2022-06-06 15:27:25 +03:00
Dmitry Stogov
054a70012e Aarch64 back-end (incomplete) 2022-06-03 12:47:02 +03:00
Dmitry Stogov
30e11861dd Aarch64 back-end (incomplete) 2022-06-03 00:38:49 +03:00
Dmitry Stogov
fb998c9058 Aarch64 back-end (incomplete) 2022-06-02 18:34:47 +03:00
Dmitry Stogov
ab8019e0cd Aarch64 back-end (incomplete) 2022-06-02 15:12:56 +03:00
Dmitry Stogov
bb842b489c Aarch64 backend support & unification 2022-06-01 18:16:32 +03:00