Dmitry Stogov
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f5bbdeea27
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Fix buffer overflow
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2022-05-26 17:19:43 +03:00 |
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Dmitry Stogov
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7e782a291a
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Extend disassembler to support .rodata section and IP relative data labels
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2022-05-26 01:17:02 +03:00 |
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Dmitry Stogov
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19e93fd3f6
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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Dmitry Stogov
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d3c1e4a02f
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Reorder basic blocks to reduce number of jumps and improve code locality
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2022-05-24 00:43:35 +03:00 |
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Dmitry Stogov
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911219493d
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Implement IJMP instruction (indirect jump or computed goto)
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2022-05-19 18:56:48 +03:00 |
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Dmitry Stogov
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bae7df6a5f
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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Dmitry Stogov
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bf369d0eac
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Swap operands for better load fusion
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2022-05-19 13:17:50 +03:00 |
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Dmitry Stogov
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c9bb858e50
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Fuse loads without register allocation when this makes sense.
Make oarameters passed through stack to reuse the same stack slot for spilling.
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2022-05-19 10:53:08 +03:00 |
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Dmitry Stogov
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cdd39f22b0
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Merge spills for VSTORE with -O0
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2022-05-18 23:12:20 +03:00 |
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Dmitry Stogov
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c5a24ff734
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Add support for instructions that modify result directly in memory
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2022-05-18 21:49:08 +03:00 |
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Dmitry Stogov
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5319951060
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Align stack once
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2022-05-17 23:01:37 +03:00 |
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Dmitry Stogov
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e794451451
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Preallocate call stack
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2022-05-17 22:37:13 +03:00 |
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Dmitry Stogov
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445dd65c78
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Improve argument passing
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2022-05-17 17:30:04 +03:00 |
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Dmitry Stogov
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4e917faaba
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Fix stack parameters loading
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2022-05-17 15:00:58 +03:00 |
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Dmitry Stogov
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1e7059d7e0
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Pass arguments through stack in reverse order
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2022-05-17 12:34:31 +03:00 |
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Dmitry Stogov
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6fb5380906
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Take into account spill slot size and alignment
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2022-05-16 22:16:29 +03:00 |
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Dmitry Stogov
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8496780ece
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Fix temporary register usage for parralel arguments passing
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2022-05-16 15:34:36 +03:00 |
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Dmitry Stogov
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a3b597feef
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Use different interval for registers clobbered by CALL
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2022-05-13 15:53:54 +03:00 |
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Dmitry Stogov
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1f673ebfda
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Better temporary register usage for SSA deconstruction
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2022-05-13 00:32:37 +03:00 |
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Dmitry Stogov
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69b5a852e5
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Make DESSA API use "ir_ref" instead of "virtual register number"
(0 - is still a temporary register)
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2022-05-06 16:19:57 +03:00 |
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Dmitry Stogov
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2403fa1edc
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Fix spill loads during argument passing
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2022-05-06 12:55:07 +03:00 |
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Dmitry Stogov
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b580c926e6
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Avoid need for temporary register for parameters loading
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2022-05-06 11:27:24 +03:00 |
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Dmitry Stogov
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89f320d7b7
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Add SWITCH support for temporary registers
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2022-05-06 10:00:19 +03:00 |
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Dmitry Stogov
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dd5a3a3b72
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Add flexible support for temporary registers.
Get rid of hardcoded temporary registers (incomplete)
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2022-05-05 22:35:39 +03:00 |
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Dmitry Stogov
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310f605d6c
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Fix register clobbering
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2022-04-26 22:49:41 +03:00 |
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Dmitry Stogov
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4a6c8d60a6
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Fix ALLOCA to align stack frame
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2022-04-22 12:55:38 +03:00 |
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Dmitry Stogov
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549ac2efd9
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Add test
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2022-04-22 11:32:59 +03:00 |
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Dmitry Stogov
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c47de38bab
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Merge spill slots for VAR, VLOAD and VSTORE (this may be unsafe)
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2022-04-22 11:30:33 +03:00 |
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Dmitry Stogov
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034ef95e07
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Allow memory update instructions (without loading into register)
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2022-04-22 01:40:10 +03:00 |
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Dmitry Stogov
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84b2bac02c
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Add more tests
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2022-04-22 00:11:34 +03:00 |
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