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148 Commits 2 Branches 0 Tags 3.2 MiB
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148 Commits

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Author SHA1 Message Date
Dmitry Stogov
4e917faaba Fix stack parameters loading 2022-05-17 15:00:58 +03:00
Dmitry Stogov
da5de8a390 Introduce IR_PREALLOCATED_STACK flag 2022-05-17 13:15:41 +03:00
Dmitry Stogov
1e7059d7e0 Pass arguments through stack in reverse order 2022-05-17 12:34:31 +03:00
Dmitry Stogov
92ba2fb534 Add support for passing arguments throug stack 
This may be improved by preallocating stack area and
better register allocation.
 2022-05-17 11:20:28 +03:00
Dmitry Stogov
55f21706c9 clenup 2022-05-17 09:09:45 +03:00
Dmitry Stogov
106f201171 Fix support for fixed registers in -O0 register allocator 2022-05-17 08:38:45 +03:00
Dmitry Stogov
fd457e3590 Fix -O0 register allocator 2022-05-17 01:47:44 +03:00
Dmitry Stogov
3e5f151502 Update tasks 2022-05-17 00:21:00 +03:00
Dmitry Stogov
0189eb28d0 Use a kind of "Buddy Allocaor" to pack spill slots of different sizes 2022-05-17 00:17:59 +03:00
Dmitry Stogov
6fb5380906 Take into account spill slot size and alignment 2022-05-16 22:16:29 +03:00
Dmitry Stogov
49374df65c Remove done and outdated tasks 2022-05-16 15:38:25 +03:00
Dmitry Stogov
8496780ece Fix temporary register usage for parralel arguments passing 2022-05-16 15:34:36 +03:00
Dmitry Stogov
f086da2550 Clenaup (remove unnecessary SHIFT case) 2022-05-16 14:36:27 +03:00
Dmitry Stogov
5f529a9d67 Hint propagation 2022-05-16 11:53:10 +03:00
Dmitry Stogov
cebcde2143 Only arguments passed on stack must be in regisers (to avoid mem->mem copy) 2022-05-16 10:50:50 +03:00
Dmitry Stogov
e8dd422167 Cleanup "top" usage 2022-05-16 10:19:30 +03:00
Dmitry Stogov
a3b597feef Use different interval for registers clobbered by CALL 2022-05-13 15:53:54 +03:00
Dmitry Stogov
e4e3336b2b Take into account registers used to pass constants 2022-05-13 15:26:11 +03:00
Dmitry Stogov
896ddb9e77 Flexable scratch register constraints (allow MUL %edx) 2022-05-13 15:10:15 +03:00
Dmitry Stogov
814d2b4b69 Initial support for indirect calls 
incomplete: live ranges should be adjusted
 2022-05-13 14:38:58 +03:00
Dmitry Stogov
f040444746 Fix incorrect temporary registers intervals for IR_CMP_AND_BRANCH_* 2022-05-13 13:16:31 +03:00
Dmitry Stogov
3dac541928 LSRA cleanup 2022-05-13 12:14:21 +03:00
Dmitry Stogov
4eaca331b9 Allow using debug_regset in RELEASE build 2022-05-13 09:22:31 +03:00
Dmitry Stogov
8895b18c0c Added task 2022-05-13 09:06:43 +03:00
Dmitry Stogov
cd6eb1354a Renumber virtual registers 2022-05-13 01:15:24 +03:00
Dmitry Stogov
1f673ebfda Better temporary register usage for SSA deconstruction 2022-05-13 00:32:37 +03:00
Dmitry Stogov
cd00ae6099 Allow spill slot fusing when swap operands of fp comparison 2022-05-12 21:58:58 +03:00
Dmitry Stogov
386b140265 Refactor Linear Scan Register Allocator to use linked lists instead of bitsets 
This fixes allocation of several temporary variables for single instruction
 2022-05-12 17:43:08 +03:00
Dmitry Stogov
1028d7d330 Fix reading behind array range 2022-05-12 11:04:20 +03:00
Dmitry Stogov
d3c4844da7 Fix reading behind array range 2022-05-12 10:57:38 +03:00
Dmitry Stogov
c2d224148b Use prefered register if possible 2022-05-11 21:10:35 +03:00
Dmitry Stogov
f8edcb9762 Fix possible crash 2022-05-11 18:18:28 +03:00
Dmitry Stogov
6d7ea2fd37 Prevent crash when dump dessa moves with -O0 2022-05-11 17:05:29 +03:00
Dmitry Stogov
4569d80218 Remove temporary test files 2022-05-06 19:19:04 +03:00
Dmitry Stogov
2580813c48 cleanup 2022-05-06 19:05:39 +03:00
Dmitry Stogov
69b5a852e5 Make DESSA API use "ir_ref" instead of "virtual register number" 
(0 - is still a temporary register)
 2022-05-06 16:19:57 +03:00
Dmitry Stogov
b2033ebaf9 Fixed parallel copy 2022-05-06 13:32:20 +03:00
Dmitry Stogov
b6ce5055e1 Fix register usage in CALL 2022-05-06 13:12:19 +03:00
Dmitry Stogov
2403fa1edc Fix spill loads during argument passing 2022-05-06 12:55:07 +03:00
Dmitry Stogov
b580c926e6 Avoid need for temporary register for parameters loading 2022-05-06 11:27:24 +03:00
Dmitry Stogov
e434c0a8aa Cleanup and add asserion for unimplemented case 2022-05-06 11:10:09 +03:00
Dmitry Stogov
9d51134813 cleanup 2022-05-06 10:37:25 +03:00
Dmitry Stogov
89f320d7b7 Add SWITCH support for temporary registers 2022-05-06 10:00:19 +03:00
Dmitry Stogov
9f1ca6b82c Add IR_LIVE_INTERVAL_TEMP and IR_LIVE_INTERVAL_VAR flags 2022-05-06 09:23:14 +03:00
Dmitry Stogov
048ff19133 cleanup 2022-05-05 23:43:16 +03:00
Dmitry Stogov
3c6e4c8b3a Use -O2 for release build 2022-05-05 22:37:25 +03:00
Dmitry Stogov
dd5a3a3b72 Add flexible support for temporary registers. 
Get rid of hardcoded temporary registers (incomplete)
 2022-05-05 22:35:39 +03:00
Dmitry Stogov
7de4566498 Add tests for 64-bit constants 2022-05-04 15:37:07 +03:00
Dmitry Stogov
1130c256ae Find optimal split position 2022-05-04 11:59:35 +03:00
Dmitry Stogov
4f294109e8 Result of PARAM may be stored into a spill slot without register 2022-05-04 09:50:23 +03:00