Dmitry Stogov
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8a5a81c03e
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Improve live interval splitting and eliminate more redundand spill loads
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2023-06-27 11:29:26 +03:00 |
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Dmitry Stogov
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678a6af863
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 14:41:01 +03:00 |
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Dmitry Stogov
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85beed7901
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Fixed incorrect oredering of moves during de-SSA
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
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2023-06-22 12:07:19 +03:00 |
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Dmitry Stogov
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35f94d570f
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Revert "Eliminate duplicate spill loads at the same basic block"
This reverts commit 5d05d78462.
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2023-06-22 01:58:26 +03:00 |
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Dmitry Stogov
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5d05d78462
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 01:24:50 +03:00 |
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Dmitry Stogov
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ffac404552
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Fix impossible load fusion
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2023-06-20 12:14:52 +03:00 |
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Dmitry Stogov
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009e9c4a53
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Split assign_regs() loop into two versions (with and without spilling).
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2023-06-20 08:34:54 +03:00 |
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Dmitry Stogov
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6a8830c1dc
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Better usage of the register hints
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2023-06-09 16:26:15 +03:00 |
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Dmitry Stogov
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b8be0b9dd9
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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Dmitry Stogov
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c9d3804b6e
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Fixed mistakes in GCM algorithm
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2023-05-29 17:02:50 +03:00 |
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Dmitry Stogov
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75edc8fec5
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Added type compatibility assertion and fixed mistakes in tests
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2023-05-22 20:48:07 +03:00 |
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Dmitry Stogov
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c9fa8dfebd
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Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
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2023-05-17 22:37:45 +03:00 |
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Dmitry Stogov
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9eb366698d
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Avoid reservaton of temporary resiser for argument passing
We may use any scratch register that is not used for parameters
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2023-04-26 12:16:05 +03:00 |
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Dmitry Stogov
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0de0c1d0fa
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Improve parallel copy algorithm to support move of single source into multiple destinations
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2023-04-26 10:56:55 +03:00 |
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Dmitry Stogov
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f85f5fd2a8
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Remove data dependency between TAILCALL and UNREACHABLE
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2023-04-13 02:41:28 +03:00 |
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Dmitry Stogov
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1e5e9e08ce
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Re-implement instruction fusion and live-range construction
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2023-04-05 19:20:43 +03:00 |
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Dmitry Stogov
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ee827ee983
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Don't create two DEF UsePos
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2023-03-29 17:22:49 +03:00 |
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Dmitry Stogov
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26e462fa42
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Add more folding rules
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2023-03-29 14:07:31 +03:00 |
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Dmitry Stogov
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24e8e216a1
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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Dmitry Stogov
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5a48805c81
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Add support for Windows-64 ABI ("home space")
Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant
TODO: ARM code maight need similar changes
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2023-03-02 13:27:01 +03:00 |
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Dmitry Stogov
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00d5e471ad
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Improve load fusion, register allocateion and code selection for ADD
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2023-02-21 22:55:47 +03:00 |
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Dmitry Stogov
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2f2fed89bb
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Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32")
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2023-02-17 18:11:13 +03:00 |
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Dmitry Stogov
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1d7ab16c2a
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Allow load fuson for CALL and TAILCALL with arguments
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2023-02-14 14:51:12 +03:00 |
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Dmitry Stogov
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2e31446e37
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Better 'jp' elimination for IR_CMP_AND_BRANCH_FP
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2023-02-07 01:57:07 +03:00 |
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Dmitry Stogov
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02104b0950
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Add XFAIL-ed test for a non-efficient register allocation that should be improved
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2023-02-07 00:06:53 +03:00 |
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Dmitry Stogov
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d26b162ffa
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Fix register clobbering during argument passing
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2022-12-26 18:27:53 +03:00 |
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Dmitry Stogov
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37dececa71
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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Dmitry Stogov
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2ff0617db6
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Perform iterative folding and DCE as a final pass of SCCP
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2022-11-08 00:41:08 +03:00 |
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Dmitry Stogov
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05fd1f971d
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Better LOAD fusion
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2022-09-21 23:54:45 +03:00 |
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Dmitry Stogov
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69a3d6fd27
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Verify type compatibility
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2022-09-02 09:50:38 +03:00 |
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Dmitry Stogov
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32198c00b7
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Reimplement JMP optimization
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2022-08-30 23:15:20 +03:00 |
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Dmitry Stogov
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fd8539e17d
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Eliminate TEST after ADD/SUB/AND/OR/XOR
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2022-08-29 22:22:30 +03:00 |
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Dmitry Stogov
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47083e0f9f
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Improve LOAD fusion
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2022-08-25 18:16:17 +03:00 |
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Dmitry Stogov
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65e1619de8
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Fuse address calculation into LOAD/STORE
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2022-08-24 16:11:04 +03:00 |
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Dmitry Stogov
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88b8731c16
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Fix incorrect condition codes
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2022-08-02 13:04:03 +03:00 |
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Dmitry Stogov
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9b25587eb6
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Compound assignment instruction fusion
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2022-06-21 17:33:57 +03:00 |
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Dmitry Stogov
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5fb115ab11
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Remove LOOP_EXIT
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2022-06-15 17:27:31 +03:00 |
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Dmitry Stogov
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c28fe2734d
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Validate operand types
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2022-06-03 11:23:05 +03:00 |
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Dmitry Stogov
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f5bbdeea27
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Fix buffer overflow
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2022-05-26 17:19:43 +03:00 |
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Dmitry Stogov
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7e782a291a
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Extend disassembler to support .rodata section and IP relative data labels
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2022-05-26 01:17:02 +03:00 |
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Dmitry Stogov
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19e93fd3f6
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Allow multi-target test suite
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2022-05-25 17:38:22 +03:00 |
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Dmitry Stogov
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d3c1e4a02f
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Reorder basic blocks to reduce number of jumps and improve code locality
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2022-05-24 00:43:35 +03:00 |
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Dmitry Stogov
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911219493d
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Implement IJMP instruction (indirect jump or computed goto)
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2022-05-19 18:56:48 +03:00 |
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Dmitry Stogov
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bae7df6a5f
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Implement code generation for MIN and MAX instructions
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2022-05-19 17:03:00 +03:00 |
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Dmitry Stogov
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bf369d0eac
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Swap operands for better load fusion
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2022-05-19 13:17:50 +03:00 |
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Dmitry Stogov
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c9bb858e50
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Fuse loads without register allocation when this makes sense.
Make oarameters passed through stack to reuse the same stack slot for spilling.
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2022-05-19 10:53:08 +03:00 |
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Dmitry Stogov
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cdd39f22b0
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Merge spills for VSTORE with -O0
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2022-05-18 23:12:20 +03:00 |
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Dmitry Stogov
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c5a24ff734
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Add support for instructions that modify result directly in memory
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2022-05-18 21:49:08 +03:00 |
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Dmitry Stogov
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5319951060
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Align stack once
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2022-05-17 23:01:37 +03:00 |
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Dmitry Stogov
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e794451451
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Preallocate call stack
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2022-05-17 22:37:13 +03:00 |
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