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09829a9e69
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72 Commits

Author SHA1 Message Date
Dmitry Stogov
09829a9e69 Fixed x86_64 calling convention for vararg functions 
%al is used as a hidden register to specify the number of passed vector registers
 2023-09-27 10:23:34 +03:00
Dmitry Stogov
0dbb794399
CI tests for MACOS build (#46) 2023-08-30 15:24:12 +03:00
Dmitry Stogov
7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
 2023-06-29 12:42:44 +03:00
Dmitry Stogov
2bfe1626ad Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator" 2023-06-28 22:00:50 +03:00
Dmitry Stogov
8a5a81c03e Improve live interval splitting and eliminate more redundand spill loads 2023-06-27 11:29:26 +03:00
Dmitry Stogov
678a6af863 Eliminate duplicate spill loads at the same basic block 2023-06-22 14:41:01 +03:00
Dmitry Stogov
85beed7901 Fixed incorrect oredering of moves during de-SSA 
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
 2023-06-22 12:07:19 +03:00
Dmitry Stogov
35f94d570f Revert "Eliminate duplicate spill loads at the same basic block" 
This reverts commit 5d05d78462.
 2023-06-22 01:58:26 +03:00
Dmitry Stogov
5d05d78462 Eliminate duplicate spill loads at the same basic block 2023-06-22 01:24:50 +03:00
Dmitry Stogov
ffac404552 Fix impossible load fusion 2023-06-20 12:14:52 +03:00
Dmitry Stogov
009e9c4a53 Split assign_regs() loop into two versions (with and without spilling). 2023-06-20 08:34:54 +03:00
Dmitry Stogov
6a8830c1dc Better usage of the register hints 2023-06-09 16:26:15 +03:00
Dmitry Stogov
b8be0b9dd9 Avoid loading of stack parameter to register if this is not necessary 2023-06-09 00:35:15 +03:00
Dmitry Stogov
c9d3804b6e Fixed mistakes in GCM algorithm 2023-05-29 17:02:50 +03:00
Dmitry Stogov
75edc8fec5 Added type compatibility assertion and fixed mistakes in tests 2023-05-22 20:48:07 +03:00
Dmitry Stogov
c9fa8dfebd Fixed SSA deconstruction 
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
 2023-05-17 22:37:45 +03:00
Dmitry Stogov
9eb366698d Avoid reservaton of temporary resiser for argument passing 
We may use any scratch register that is not used for parameters
 2023-04-26 12:16:05 +03:00
Dmitry Stogov
0de0c1d0fa Improve parallel copy algorithm to support move of single source into multiple destinations 2023-04-26 10:56:55 +03:00
Dmitry Stogov
f85f5fd2a8 Remove data dependency between TAILCALL and UNREACHABLE 2023-04-13 02:41:28 +03:00
Dmitry Stogov
1e5e9e08ce Re-implement instruction fusion and live-range construction 2023-04-05 19:20:43 +03:00
Dmitry Stogov
ee827ee983 Don't create two DEF UsePos 2023-03-29 17:22:49 +03:00
Dmitry Stogov
26e462fa42 Add more folding rules 2023-03-29 14:07:31 +03:00
Dmitry Stogov
24e8e216a1 Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
Dmitry Stogov
5a48805c81 Add support for Windows-64 ABI ("home space") 
Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant

TODO: ARM code maight need similar changes
 2023-03-02 13:27:01 +03:00
Dmitry Stogov
00d5e471ad Improve load fusion, register allocateion and code selection for ADD 2023-02-21 22:55:47 +03:00
Dmitry Stogov
2f2fed89bb Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32") 2023-02-17 18:11:13 +03:00
Dmitry Stogov
1d7ab16c2a Allow load fuson for CALL and TAILCALL with arguments 2023-02-14 14:51:12 +03:00
Dmitry Stogov
2e31446e37 Better 'jp' elimination for IR_CMP_AND_BRANCH_FP 2023-02-07 01:57:07 +03:00
Dmitry Stogov
02104b0950 Add XFAIL-ed test for a non-efficient register allocation that should be improved 2023-02-07 00:06:53 +03:00
Dmitry Stogov
d26b162ffa Fix register clobbering during argument passing 2022-12-26 18:27:53 +03:00
Dmitry Stogov
37dececa71 Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
Dmitry Stogov
2ff0617db6 Perform iterative folding and DCE as a final pass of SCCP 2022-11-08 00:41:08 +03:00
Dmitry Stogov
05fd1f971d Better LOAD fusion 2022-09-21 23:54:45 +03:00
Dmitry Stogov
69a3d6fd27 Verify type compatibility 2022-09-02 09:50:38 +03:00
Dmitry Stogov
32198c00b7 Reimplement JMP optimization 2022-08-30 23:15:20 +03:00
Dmitry Stogov
fd8539e17d Eliminate TEST after ADD/SUB/AND/OR/XOR 2022-08-29 22:22:30 +03:00
Dmitry Stogov
47083e0f9f Improve LOAD fusion 2022-08-25 18:16:17 +03:00
Dmitry Stogov
65e1619de8 Fuse address calculation into LOAD/STORE 2022-08-24 16:11:04 +03:00
Dmitry Stogov
88b8731c16 Fix incorrect condition codes 2022-08-02 13:04:03 +03:00
Dmitry Stogov
9b25587eb6 Compound assignment instruction fusion 2022-06-21 17:33:57 +03:00
Dmitry Stogov
5fb115ab11 Remove LOOP_EXIT 2022-06-15 17:27:31 +03:00
Dmitry Stogov
c28fe2734d Validate operand types 2022-06-03 11:23:05 +03:00
Dmitry Stogov
f5bbdeea27 Fix buffer overflow 2022-05-26 17:19:43 +03:00
Dmitry Stogov
7e782a291a Extend disassembler to support .rodata section and IP relative data labels 2022-05-26 01:17:02 +03:00
Dmitry Stogov
19e93fd3f6 Allow multi-target test suite 2022-05-25 17:38:22 +03:00
Dmitry Stogov
d3c1e4a02f Reorder basic blocks to reduce number of jumps and improve code locality 2022-05-24 00:43:35 +03:00
Dmitry Stogov
911219493d Implement IJMP instruction (indirect jump or computed goto) 2022-05-19 18:56:48 +03:00
Dmitry Stogov
bae7df6a5f Implement code generation for MIN and MAX instructions 2022-05-19 17:03:00 +03:00
Dmitry Stogov
bf369d0eac Swap operands for better load fusion 2022-05-19 13:17:50 +03:00
Dmitry Stogov
c9bb858e50 Fuse loads without register allocation when this makes sense. 
Make oarameters passed through stack to reuse the same stack slot for spilling.
 2022-05-19 10:53:08 +03:00