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414 Commits 2 Branches 0 Tags 3.2 MiB
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62 Commits

Author SHA1 Message Date
Dmitry Stogov
45fff1fe5f Implement binding IR node to VAR (assign spill slot) 2022-09-20 11:03:25 +03:00
Dmitry Stogov
6973c76f64 Update tasks 2022-08-23 19:00:47 +03:00
Dmitry Stogov
3e1816a71f Fix register allocation for ABS_INT 2022-05-27 00:11:31 +03:00
Dmitry Stogov
8683331d60 Update tasks 2022-05-26 21:19:42 +03:00
Dmitry Stogov
4974c301bc Fix code generation for preserved registers and dessa moves 2022-05-26 18:08:39 +03:00
Dmitry Stogov
62d7fa7147 Fix string argument passing 2022-05-26 16:34:01 +03:00
Dmitry Stogov
e28a3c801e Fix retutn FP numbers for 32-bit x86 back-end 2022-05-26 11:58:51 +03:00
Dmitry Stogov
7e782a291a Extend disassembler to support .rodata section and IP relative data labels 2022-05-26 01:17:02 +03:00
Dmitry Stogov
ead2b69fc6 x86_32 backend (incomplete) 2022-05-25 22:00:18 +03:00
Dmitry Stogov
4747a22474 Update tasks 2022-05-25 12:04:33 +03:00
Dmitry Stogov
ddd5b739db Update tasks 2022-05-24 12:59:57 +03:00
Dmitry Stogov
596f03f263 Update tasks 2022-05-23 19:34:09 +03:00
Dmitry Stogov
fa36dbf9af Update tasks 2022-05-20 13:09:41 +03:00
Dmitry Stogov
c6b0e95d6b Add type conversion nodes (no code generation yet) 2022-05-20 01:01:48 +03:00
Dmitry Stogov
41a76b39d8 update tasks 2022-05-19 22:12:20 +03:00
Dmitry Stogov
911219493d Implement IJMP instruction (indirect jump or computed goto) 2022-05-19 18:56:48 +03:00
Dmitry Stogov
bae7df6a5f Implement code generation for MIN and MAX instructions 2022-05-19 17:03:00 +03:00
Dmitry Stogov
8ccb7bc13a Implement overflow checks 2022-05-19 15:49:47 +03:00
Dmitry Stogov
bf369d0eac Swap operands for better load fusion 2022-05-19 13:17:50 +03:00
Dmitry Stogov
58063dd470 Update tasks 2022-05-19 11:02:39 +03:00
Dmitry Stogov
c9bb858e50 Fuse loads without register allocation when this makes sense. 
Make oarameters passed through stack to reuse the same stack slot for spilling.
 2022-05-19 10:53:08 +03:00
Dmitry Stogov
c5a24ff734 Add support for instructions that modify result directly in memory 2022-05-18 21:49:08 +03:00
Dmitry Stogov
96fc0fb520 Allow passing arguments from MEM to MEM 2022-05-18 10:07:48 +03:00
Dmitry Stogov
e794451451 Preallocate call stack 2022-05-17 22:37:13 +03:00
Dmitry Stogov
f08386b379 Update tasks 2022-05-17 15:04:32 +03:00
Dmitry Stogov
3e5f151502 Update tasks 2022-05-17 00:21:00 +03:00
Dmitry Stogov
49374df65c Remove done and outdated tasks 2022-05-16 15:38:25 +03:00
Dmitry Stogov
8496780ece Fix temporary register usage for parralel arguments passing 2022-05-16 15:34:36 +03:00
Dmitry Stogov
5f529a9d67 Hint propagation 2022-05-16 11:53:10 +03:00
Dmitry Stogov
f040444746 Fix incorrect temporary registers intervals for IR_CMP_AND_BRANCH_* 2022-05-13 13:16:31 +03:00
Dmitry Stogov
8895b18c0c Added task 2022-05-13 09:06:43 +03:00
Dmitry Stogov
1f673ebfda Better temporary register usage for SSA deconstruction 2022-05-13 00:32:37 +03:00
Dmitry Stogov
dd5a3a3b72 Add flexible support for temporary registers. 
Get rid of hardcoded temporary registers (incomplete)
 2022-05-05 22:35:39 +03:00
Dmitry Stogov
1130c256ae Find optimal split position 2022-05-04 11:59:35 +03:00
Dmitry Stogov
3e6f84eef4 Add "must be in reg" constraint 2022-04-28 14:48:43 +03:00
Dmitry Stogov
240259adf8 add task 2022-04-28 09:23:02 +03:00
Dmitry Stogov
99e2b4c3fd Remove done and add new tasks 2022-04-22 13:31:28 +03:00
Dmitry Stogov
4a6c8d60a6 Fix ALLOCA to align stack frame 2022-04-22 12:55:38 +03:00
Dmitry Stogov
5cb0af8cd9 Support for compound assignment instructions 2022-04-22 12:11:30 +03:00
Dmitry Stogov
ea77ea27cb Improve code for commutative instructions 
(ir_last_use() may be incomplete)
 2022-04-21 21:47:00 +03:00
Dmitry Stogov
139b49c6ea Update tasks 2022-04-21 10:20:41 +03:00
Dmitry Stogov
6f3cc3052c Implement ABS for C code generator 
Remove POW
 2022-04-21 01:00:46 +03:00
Dmitry Stogov
506e7b658f Implement ABS and NEG 2022-04-21 00:31:28 +03:00
Dmitry Stogov
705f0f1e1d VADDR instruction 2022-04-20 12:00:36 +03:00
Dmitry Stogov
81852e6536 Separate tasks 2022-04-20 10:03:00 +03:00
Dmitry Stogov
51daf5556c Initial support for ALLOCA, LOAD and STORE (incomplete) 2022-04-19 23:42:05 +03:00
Dmitry Stogov
6b60d8fba9 Code generation for VLOAD and VSTORE 2022-04-19 22:35:29 +03:00
Dmitry Stogov
7e9d1d7dba Improve VLOAD/VSTORE support in C code generator 2022-04-19 17:14:44 +03:00
Dmitry Stogov
a1366ebd92 Use zero-extended load if possible 2022-04-19 14:18:39 +03:00
Dmitry Stogov
207dca73e8 64-bit constants support 2022-04-19 14:11:07 +03:00