Dmitry Stogov
1d7ab16c2a
Allow load fuson for CALL and TAILCALL with arguments
2023-02-14 14:51:12 +03:00
Dmitry Stogov
2e31446e37
Better 'jp' elimination for IR_CMP_AND_BRANCH_FP
2023-02-07 01:57:07 +03:00
Dmitry Stogov
02104b0950
Add XFAIL-ed test for a non-efficient register allocation that should be improved
2023-02-07 00:06:53 +03:00
Dmitry Stogov
54597bc862
Clear destination regeister before INT to FP conversion to avoid partial register stall
2022-12-28 00:05:23 +03:00
Dmitry Stogov
67da9e93ea
Fix register clobbering during argument passing and spill load
2022-12-26 20:25:11 +03:00
Dmitry Stogov
d26b162ffa
Fix register clobbering during argument passing
2022-12-26 18:27:53 +03:00
Dmitry Stogov
95729f76bf
Use IMUL instead of MUL
2022-12-16 12:57:40 +03:00
Dmitry Stogov
efbc51baaa
Fixed codegeneration for TRUNC on aarch64
2022-12-07 11:56:53 +03:00
Dmitry Stogov
daf659a457
Fix incorrect conditions
2022-12-01 00:43:42 +03:00
Dmitry Stogov
c6aeb417fa
Extend test suite to support XFAIL section
2022-11-22 10:43:29 +03:00
Dmitry Stogov
3e3746d5cb
Refactor API that expose target CPU register constraints for register allocator
2022-11-17 23:30:35 +03:00
Dmitry Stogov
05127b1b13
Remove duplicate code and allow load fusion of IR_SHIFT.op2
2022-11-16 13:20:58 +03:00
Dmitry Stogov
673779ba6a
Use IR_COPY_INT/FP rule instead of IR_COPY op
2022-11-16 12:55:40 +03:00
Dmitry Stogov
4c536aae20
Extend SCCP to perform Dead Load Elimination
2022-11-08 15:39:00 +03:00
Dmitry Stogov
37dececa71
Add more tests (8 tests ara failed on 32-bit x86)
2022-11-08 11:56:22 +03:00
Dmitry Stogov
2ff0617db6
Perform iterative folding and DCE as a final pass of SCCP
2022-11-08 00:41:08 +03:00
Dmitry Stogov
924f5949f2
Fixed SSE operands alignment and 32-bit support
2022-09-27 20:36:34 +03:00
Dmitry Stogov
05fd1f971d
Better LOAD fusion
2022-09-21 23:54:45 +03:00
Dmitry Stogov
69a3d6fd27
Verify type compatibility
2022-09-02 09:50:38 +03:00
Dmitry Stogov
32198c00b7
Reimplement JMP optimization
2022-08-30 23:15:20 +03:00
Dmitry Stogov
0596de2291
Fuse LOAD into IMULL/3
2022-08-30 11:26:38 +03:00
Dmitry Stogov
fd8539e17d
Eliminate TEST after ADD/SUB/AND/OR/XOR
2022-08-29 22:22:30 +03:00
Dmitry Stogov
47083e0f9f
Improve LOAD fusion
2022-08-25 18:16:17 +03:00
Dmitry Stogov
65e1619de8
Fuse address calculation into LOAD/STORE
2022-08-24 16:11:04 +03:00
Dmitry Stogov
32e045d93e
typo
2022-08-23 17:02:34 +03:00
Dmitry Stogov
88b8731c16
Fix incorrect condition codes
2022-08-02 13:04:03 +03:00
Dmitry Stogov
9b25587eb6
Compound assignment instruction fusion
2022-06-21 17:33:57 +03:00
Dmitry Stogov
5fb115ab11
Remove LOOP_EXIT
2022-06-15 17:27:31 +03:00
Dmitry Stogov
c28fe2734d
Validate operand types
2022-06-03 11:23:05 +03:00
Dmitry Stogov
ab8019e0cd
Aarch64 back-end (incomplete)
2022-06-02 15:12:56 +03:00
Dmitry Stogov
bb842b489c
Aarch64 backend support & unification
2022-06-01 18:16:32 +03:00
Dmitry Stogov
f5bbdeea27
Fix buffer overflow
2022-05-26 17:19:43 +03:00
Dmitry Stogov
7e782a291a
Extend disassembler to support .rodata section and IP relative data labels
2022-05-26 01:17:02 +03:00
Dmitry Stogov
19e93fd3f6
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
Dmitry Stogov
463002107a
Rename "gcm_blocks" into "cfg_map"
2022-05-25 09:33:47 +03:00
Dmitry Stogov
04667faf22
Reorder blocks according to branch probability
2022-05-24 12:47:39 +03:00
Dmitry Stogov
d3c1e4a02f
Reorder basic blocks to reduce number of jumps and improve code locality
2022-05-24 00:43:35 +03:00
Dmitry Stogov
6f7f7b1268
Implement code generation for type conversion instructions
...
Register constraints might need to be tweeked.
2022-05-20 13:07:41 +03:00
Dmitry Stogov
c464b123cb
Add test for TRUNC
2022-05-20 09:09:52 +03:00
Dmitry Stogov
d250f77713
Improve type conversion nodes
2022-05-20 09:00:13 +03:00
Dmitry Stogov
c6b0e95d6b
Add type conversion nodes (no code generation yet)
2022-05-20 01:01:48 +03:00
Dmitry Stogov
911219493d
Implement IJMP instruction (indirect jump or computed goto)
2022-05-19 18:56:48 +03:00
Dmitry Stogov
bae7df6a5f
Implement code generation for MIN and MAX instructions
2022-05-19 17:03:00 +03:00
Dmitry Stogov
bf369d0eac
Swap operands for better load fusion
2022-05-19 13:17:50 +03:00
Dmitry Stogov
c9bb858e50
Fuse loads without register allocation when this makes sense.
...
Make oarameters passed through stack to reuse the same stack slot for spilling.
2022-05-19 10:53:08 +03:00
Dmitry Stogov
88ab04a3c2
New tests
2022-05-18 23:53:16 +03:00
Dmitry Stogov
cdd39f22b0
Merge spills for VSTORE with -O0
2022-05-18 23:12:20 +03:00
Dmitry Stogov
c5a24ff734
Add support for instructions that modify result directly in memory
2022-05-18 21:49:08 +03:00
Dmitry Stogov
5319951060
Align stack once
2022-05-17 23:01:37 +03:00
Dmitry Stogov
e794451451
Preallocate call stack
2022-05-17 22:37:13 +03:00
Dmitry Stogov
445dd65c78
Improve argument passing
2022-05-17 17:30:04 +03:00
Dmitry Stogov
4e917faaba
Fix stack parameters loading
2022-05-17 15:00:58 +03:00
Dmitry Stogov
1e7059d7e0
Pass arguments through stack in reverse order
2022-05-17 12:34:31 +03:00
Dmitry Stogov
6fb5380906
Take into account spill slot size and alignment
2022-05-16 22:16:29 +03:00
Dmitry Stogov
8496780ece
Fix temporary register usage for parralel arguments passing
2022-05-16 15:34:36 +03:00
Dmitry Stogov
f086da2550
Clenaup (remove unnecessary SHIFT case)
2022-05-16 14:36:27 +03:00
Dmitry Stogov
a3b597feef
Use different interval for registers clobbered by CALL
2022-05-13 15:53:54 +03:00
Dmitry Stogov
896ddb9e77
Flexable scratch register constraints (allow MUL %edx)
2022-05-13 15:10:15 +03:00
Dmitry Stogov
1f673ebfda
Better temporary register usage for SSA deconstruction
2022-05-13 00:32:37 +03:00
Dmitry Stogov
69b5a852e5
Make DESSA API use "ir_ref" instead of "virtual register number"
...
(0 - is still a temporary register)
2022-05-06 16:19:57 +03:00
Dmitry Stogov
2403fa1edc
Fix spill loads during argument passing
2022-05-06 12:55:07 +03:00
Dmitry Stogov
b580c926e6
Avoid need for temporary register for parameters loading
2022-05-06 11:27:24 +03:00
Dmitry Stogov
89f320d7b7
Add SWITCH support for temporary registers
2022-05-06 10:00:19 +03:00
Dmitry Stogov
dd5a3a3b72
Add flexible support for temporary registers.
...
Get rid of hardcoded temporary registers (incomplete)
2022-05-05 22:35:39 +03:00
Dmitry Stogov
7de4566498
Add tests for 64-bit constants
2022-05-04 15:37:07 +03:00
Dmitry Stogov
310f605d6c
Fix register clobbering
2022-04-26 22:49:41 +03:00
Dmitry Stogov
4a6c8d60a6
Fix ALLOCA to align stack frame
2022-04-22 12:55:38 +03:00
Dmitry Stogov
549ac2efd9
Add test
2022-04-22 11:32:59 +03:00
Dmitry Stogov
c47de38bab
Merge spill slots for VAR, VLOAD and VSTORE (this may be unsafe)
2022-04-22 11:30:33 +03:00
Dmitry Stogov
034ef95e07
Allow memory update instructions (without loading into register)
2022-04-22 01:40:10 +03:00
Dmitry Stogov
84b2bac02c
Add more tests
2022-04-22 00:11:34 +03:00
Dmitry Stogov
6f3cc3052c
Implement ABS for C code generator
...
Remove POW
2022-04-21 01:00:46 +03:00
Dmitry Stogov
506e7b658f
Implement ABS and NEG
2022-04-21 00:31:28 +03:00
Dmitry Stogov
ffdb53821d
Refactor constraint model
...
Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE.
Hardware constraints are modeled conectiong live intervals and fixed
intervals to different sub-positions.
2022-04-20 18:53:15 +03:00
Dmitry Stogov
e449345514
Fix few CSSP bugs
2022-04-19 16:45:03 +03:00
Dmitry Stogov
0922b7cd7f
Add vreg hints
2022-04-15 16:02:23 +03:00
Dmitry Stogov
f04433999f
Reload loading to avoid register clobbering
2022-04-15 15:22:17 +03:00
Dmitry Stogov
3cb707522f
Allocate scratch (caller-saved) registers first
2022-04-15 14:22:35 +03:00
Dmitry Stogov
2c2f2dabab
Better use placement
2022-04-15 00:35:02 +03:00
Dmitry Stogov
3f6a6aa3ea
Better CPU constraint model and initial support for live interval splitting (incomplete)
2022-04-14 22:40:13 +03:00
Dmitry Stogov
d8e7a8579f
Use LEA for 32-bit integers
2022-04-14 18:11:43 +03:00
Dmitry Stogov
9ccefcf973
Support for more instruction in C backend and BOOL_NOT in x86_86
2022-04-08 19:02:11 +03:00
Dmitry Stogov
f1cc9a4ddb
Added tests for unary integer instructions
2022-04-08 16:40:28 +03:00
Dmitry Stogov
fa7a34c629
Support for unordered floating point comparison
2022-04-08 15:29:05 +03:00
Dmitry Stogov
552aeec7d5
x86_64: Optimize integer comparison with zero
2022-04-08 10:49:22 +03:00
Dmitry Stogov
0f92e7dc67
Added more x86_64 tests for integer comparison
2022-04-08 10:05:42 +03:00
Dmitry Stogov
67b23a95b5
Added x86_64 tests for integer comparison
2022-04-08 00:59:45 +03:00
Dmitry Stogov
14f4fdf29d
Added few more basic x86_64 tests
2022-04-08 00:29:49 +03:00
Dmitry Stogov
baf3d31526
ws
2022-04-07 23:31:03 +03:00
Dmitry Stogov
a28f18a712
Added few basic x86_64 tests
2022-04-07 23:24:29 +03:00
Dmitry Stogov
5b34386f62
Register Allocator suppor for fixed registers, use positions and register hints (incomplete).
2022-04-07 11:11:57 +03:00
Dmitry Stogov
2937993190
Initial import
2022-04-06 00:19:23 +03:00